MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 843

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.2.4
The Device Controller Interface Version (USB_DCIVERSION) register contains a BCD encoding of the
device controller interface. The most-significant byte of the register represents a major revision and the
least-significant byte is the minor revision.
Table 32-12
the EHCI specification.
Freescale Semiconductor
Address: Base + 0x120
Reset
Reset
EECP
Field
ADC
ASP
PFL
IST
W
W
R
R
16
0
0
0
0
provides bit descriptions for the USB_DCIVERSION register. This register is not defined in
Device Controller Interface Version (USB_DCIVERSION) Register
(Non-EHCI)
Figure 32-12. Device Controller Interface Version (USB_DCIVERSION) Register
EHCI Extended Capabilities Pointer. This optional field indicates existence of a capabilities list. A value of 0x00
indicates no extended capabilities are implemented. A non-zero value in this register indicates the offset in
PCI configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field always reads 0.
Isochronous Scheduling Threshold. This field indicates, relative to the current position of the executing host
controller, where software can reliably update the isochronous schedule. When bit [7] is 0, the value of the
least significant three bits indicates the number of microframes a host controller can hold a set of isochronous
data structures (one or more) before flushing the state. When bit [7] is a 1, host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field always reads 0.
Asynchronous Schedule Park Capability. This bit indicates if the host controller supports the park feature for
high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and set to a
specific level by using the asynchronous schedule park mode enable and asynchronous schedule park mode
count fields in the USB_USBCMD register.
This field is always 1 (park feature supported).
Programmable Frame List Flag. This bit indicates system software can specify and use a frame list length less
that 1024 elements. Frame list size is configured via the USB_USBCMD register frame list size field. The
frame list must always be aligned on a 4K page boundary. This requirement ensures the frame list is always
physically contiguous.
This field always reads 1.
64-Bit Addressing Capability. This field always reads 0. Only 32-bit addressing is supported.
17
0
0
0
1
18
0
0
0
2
Table 32-11. USB_HCCPARAMS field descriptions
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
21
0
0
0
5
Figure 32-12
22
0
0
0
6
DCIVERSION
23
0
0
0
7
Description
shows the USB_DCIVERSION register.
24
8
0
0
0
25
9
0
0
0
Universal Serial Bus Interface with On-The-Go
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Access: User read-only
13
29
0
0
0
14
30
0
0
0
32-15
15
31
0
0
1