MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 510

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
19-18
Address: Base + 0x0C (I2C_MSR1)
Reset
Reset
Field
AAS
CF
BB
AL
W
W
R
R
Base + 0x2C (I2C_MSR2)
Base + 0x4C (I2C_MSR3)
CF
16
1
0
0
0
Data transferring. Bit clears while 1byte of data is being transferred. This bit is set by the falling edge of ninth
clock of a byte transfer.
0 Transfer in progress.
1 Transfer complete.
Addressed As Slave. Bit sets when its own specific address (I
address. The CPU is interrupted provided IEN is set. The CPU needs to check the SRW bit and set its Tx/Rx
mode accordingly. Writing to the I
0 Not addressed.
1 Addressed as a slave.
Bus Busy. Bit indicates bus status. When a START signal is detected, BB is set. If a STOP signal is detected,
it is cleared.
0 Bus is idle.
1 Bus is busy.
Arbitration Lost.Hardware sets the bit when the arbitration procedure is lost. Arbitration is lost in the following
circumstances:
0 No arbitration lost.
1 Arbitration lost.
Software must clear this bit by writing 0 in the interrupt routine after detecting arbitration lost and interrupt flag
(IF) bit is asserted.
AAS
• SDA sampled low when master drives high during an address or data Tx cycle.
• SDA sampled low when master drives high during a data Rx cycle acknowledge bit.
• Start cycle is attempted when bus is busy.
• A repeated start cycle is requested in slave mode.
• Stop condition is detected when not requested by master.
17
0
0
0
1
2
C)
BB
18
0
0
0
2
AL
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 19-12. I
Table 19-8. I2C_MSRn field descriptions
AKF
20
4
0
0
0
SRW
21
0
0
0
5
2
C control register clears this bit.
2
C Status Register (I2C_MSRn)
IF
22
0
0
0
6
RXAK
23
0
0
0
7
Description
24
8
0
0
0
0
25
2
9
0
0
0
0
C Address Register) is matched with the calling
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
15
31
0
0
0
0