MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 319

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.2.2.2
11.3.2.2.3
The DDR_TIME_CONFIG1 and DDR_TIME_CONFIG2 registers need to be programmed with the
DDR1/DDR2 timing parameters. All times are given in clock cycles.
The timing parameters are conceived so the controller CSB clock cycles match with the JEDEC DDR2
specification. To interface with DDR1 or Mobile-DDR (LPDDR), some timing parameters need not be
enforced, or are calculated differently. Refer to the DRAM datasheet to determine their value. The timing
parameters need to be programmed in function of this DRAM requirement.
Freescale Semiconductor
Address: Base + 0x0008
Address: Base + 0x000C
DRAM_TIME_RFC
Timing Parameter
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
16
DRAM_TIME_RCD[3:0]
16
0
0
0
0
0
0
DRAM_TIME_RRD[4:0]
DDR Time Configuration Register 1 (DDR_TIME_CONFIG1)
DDR Time Configuration Register 2 (DDR_TIME_CONFIG2)
DRAM_TIME_RFC[5:0]
17
17
0
0
0
0
1
1
Figure 11-5. DDR Time Configuration Register 1 (DDR_TIME_CONFIG1)
Figure 11-6. DDR Time Configuration Register 2 (DDR_TIME_CONFIG2)
DRAM_TIME_RTP[4:0]
Controls JEDEC
(JEDEC spec)
Parameter
18
18
0
0
0
0
2
2
t
RFC
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
4
0
0
Table 11-9. Timing Parameters
DRAM_TIME_FAW[4:0]
DRAM_TIME_RFC = t
(All times in CSB clock
21
21
0
0
0
0
5
5
Formulae
periods)
22
22
0
0
0
0
6
6
DRAM_TIME_RC[5:0]
DRAM_TIME_WR1[4:0]
DRAM_TIME_RP[4:0]
23
23
0
0
0
0
7
7
RFC
24
24
8
0
0
8
0
0
REFRESH to ACTIVE or REFRESH to REFRESH
command interval.
DRAM_TIME_RTW1[3:0]
25
25
9
0
0
9
0
0
10
26
10
26
0
0
0
0
Table 11-9
DRAM_TIME_WTR1[3:0]
11
27
11
27
0
0
0
0
Description
DRAM_TIME_RAS[4:0]
DRAM_TIME_RPA[4:0]
12
28
12
28
0
0
0
0
Access: User read/write
Access: User read/write
gives the details.
DRAM_TIME_CCD
13
29
13
29
0
0
0
0
DRAM Controller
[3:1]
14
30
14
30
0
0
0
0
DRAM
_TIME
_RRD
11-11
[5]
15
31
15
31
0
0
0
0