MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 881

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.2.4.27 USB General Control (USB_USBGENCTRL) Register (Non-EHCI)
The USB General Control (USB_USBGENCTRL) register is shown in
big endian byte ordering. This register is not defined in the EHCI specification.
Freescale Semiconductor
Field
RXE
RXR
RXD
RXS
RXT
RXI
RX Endpoint Enable.
0 Disabled.
1 Enabled.
RX Data Toggle Reset. When a configuration event is received for this endpoint, software must write a 1 to
this bit to synchronize the data PIDs between the host and device.
RX Data Toggle Inhibit. This bit is used only for test and should always be written as 0. Writing a 1 to this bit
causes this endpoint to ignore the data toggle sequence and always accepts data packets regardless of their
data PID.
0 PID Sequencing Disabled.
1 PID Sequencing Enabled.
RX Endpoint type.
00 Control.
01 Isochronous.
10 Bulk.
11 Interrupt.
RX Endpoint Data Sink. This bit should always be written as 0, which selects the dual port memory/DMA
engine as the sink.
RX Endpoint Stall. This bit is set automatically upon receipt of a SETUP request if this endpoint is not
configured as a control endpoint. It is cleared automatically upon receipt of a SETUP request if this endpoint
is configured as a control endpoint,
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. It continues
returning STALL until this bit is cleared by software or automatically cleared as above.
Software can write a 1 to this bit to force the endpoint to return a STALL handshake to the host. This control
continues to STALL until this bit is cleared by software or automatically cleared as above for control endpoints.
Note: [Control endpoint types only] There is a slight delay (50 clocks max.) between the associated bit in the
0 Endpoint OK.
1 Endpoint Stalled.
USB_ENDPTSETUPSTAT register being cleared and hardware continuing to clear this bit. In most
systems, it is unlikely the DCD software observeS this delay. However, should the DCD observe that
the stall bit is not set after writing a 1 to it, follow this procedure: continually write this stall bit until it is
set or until a new setup has been received by checking the associated bit in the
USB_ENDPTSETUPSTAT register.
Table 32-41. USB_ENDPTCTRLn field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Universal Serial Bus Interface with On-The-Go
Figure
32-41. This register uses
32-53