MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 960

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.11.3.2 Tracking Split Transaction Progress for Isochronous Transfers
Isochronous endpoints do not employ the concept of a halt on error; however, the host controller does
identify and report per-packet errors observed in the data stream. This includes schedule traversal
problems (skipped micro-frames), timeouts, and corrupted data received.
In similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in
the micro-frames they are scheduled. The queue head data structure that manages full- and low-speed
interrupt has several mechanisms for tracking when portions of a transaction have occurred. Isochronous
transfers use siTDs for their transfers and the data structures are only reachable using the schedule in the
exact micro-frame in which they are required (so all the mechanism employed for tracking in queue heads
is not required for siTDs). Software has the option of reusing siTD several times in the complete periodic
schedule. However, it must ensure that the results of split transaction N are consumed and the siTD
re-initialized (activated) before the host controller gets back to the siTD (in a future micro-frame).
Split-transaction isochronous OUTs utilize a low-level protocol to indicate which portions of the split
transaction data have arrived. Control over the low-level protocol is exposed in an siTD using the fields
transaction position (TP) and transaction count (T-count). If the entire data payload for the OUT split
transaction is larger than 188 bytes, there is more than one start-split transaction, each of which requires
proper annotation. If host hold-offs occur, the sequence of annotations received from the host is not
complete, which is detected and managed by the transaction translator. See
Transaction Scheduling Mechanisms for Isochronous Transactions,”
are used during a sequence of start-split transactions.
The fields siTD[T-Count] and siTD[TP] are used by the host controller to drive and sequence the
transaction position annotations. It is the responsibility of system software to properly initialize these
fields in each siTD. After the budget for a split-transaction isochronous endpoint is established, S-mask,
T-Count, and TP initialization values for all the siTD associated with the endpoint are constant. They
remain constant until the budget for the endpoint is recalculated by software and the periodic schedule
adjusted.
For IN-endpoints, the transaction translator simply annotates the response data packets with enough
information to allow the host controller to identify the last data. As with split-transaction interrupt, it is the
host controller's responsibility to detect when it has missed an opportunity to execute a complete-split. The
following field in the siTD is used to track and detect errors in the execution of a split transaction for an
IN isochronous endpoint.
32-132
•
impossible to discriminate between cases 2a and 2b, which has significant impact on the
complexity of the host controller.
C-prog-mask. This is an 8-bit bit-vector where the host controller keeps track of which
complete-splits have been executed. Due to the nature of the transaction translator periodic
pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when
the complete-splits have not been executed in order. This can only occur due to system hold-offs
where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple
bit-vector that the host controller sets a bit for each complete-split executed. The bit position is
determined by the micro-frame (USB_FRINDEX[2:0]) number in which the complete-split was
executed. The host controller always checks C-prog-mask before executing a complete-split
MPC5125 Microcontroller Reference Manual, Rev. 2
for a description on how these fields
Section 32.6.11.3.1, “Split
Freescale Semiconductor