MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 878

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.25 Endpoint Control Register 0 (USB_ENDPTCTRL0)
Every device implements endpoint 0 as a control endpoint. This register is not defined in the EHCI
specification.
32-50
Address: Base + 0x1C0
Reset
Reset
ETCE
ERCE
Field
W
W
R
R
16
0
0
0
0
0
Endpoint Transmit Complete Event. Each bit indicates a transmit event (IN/INTERRUPT) occurred and
software should read the corresponding endpoint queue to determine the endpoint status. If the
corresponding IOC bit is set in the transfer descriptor, this bit is set simultaneously with the USBINT. Writing
a 1 clears the corresponding bit in this register.
ETCE[3]—Endpoint #3
ETCE[2]—Endpoint #2
ETCE[1]—Endpoint #1
ETCE[0]—Endpoint #0
Endpoint Receive Complete Event. Each bit indicates a received event (OUT/SETUP) occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the corresponding IOC bit
is set in the transfer descriptor, this bit is set simultaneously with the USBINT. Writing a 1 clears the
corresponding bit in this register.
ERCE[3]—Endpoint #3
ERCE[2]—Endpoint #2
ERCE[1]—Endpoint #1
ERCE[0]—Endpoint #0
17
0
0
0
0
1
Figure 32-39. Endpoint Control Register 0 (USB_ENDPTCTRL0)
18
0
0
0
0
2
Table 32-39. USB_ENDPTCOMPLETE field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
RXE
TXE
24
8
1
1
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
Freescale Semiconductor
Access: User read/write
RXT
TXT
13
29
0
0
14
30
0
0
0
0
RXS
TXS
15
31
0
0