MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 389

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.4
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC
(shown in
14.4.1
Initialize portions of the FEC prior to setting the ETHER_EN bit of the ETH_ECNTRL register. The exact
values depend on the particular application. The sequence is not important. Ethernet MAC registers
requiring initialization are as follows:
Freescale Semiconductor
Address: Base + 0x1F4
DMA_REV
DESC_BO
Reset
Reset
DATA_BO
•
•
•
Field
W
W
R DATA_
R
Start FEC Clock (SCCR1[FECn_EN]). See
(SCCR1).”
Initialize ETH_IMASK. See
Clear ETH_IEVENT (write 0xFFFF_FFFF). See
(ETH_IEVENT).”
Initialization Information
B0
—
Figure
16
0
0
0
Initialization Prior to Asserting ETHER_EN
DESC
The byte order control for data DMA transfers.
0 Little endian (bytes 0 and 3 swapped, bytes 1 and 2 swapped).
1 Big endian (no byte swapping).
Note: This bit is not affected by reset and must be initialized before using the DMA controller.
The byte order control for descriptor DMA transfers.
0 Little endian (bytes 0 and 3 swapped, bytes 1 and 2 swapped).
1 Big endian (no byte swapping).
Note: The DATA_BO and DESC_BO fields are muxed to generate the IPM_BO signal on the master interface.
Note: This bit is not affected by reset and must be initialized before using the DMA controller.
DMA revision; read only
_B0
—
17
0
0
1
14-1), and which locations must be initialized prior to enabling FEC.
Figure 14-27. DMA Function Control (ETH_DMA_CONTROL) Register
18
0
0
0
0
2
Table 14-31. ETH_DMA_CONTROL field descriptions
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
0
Section 14.3.5.3, “Interrupt Mask (ETH_IMASK) Register.”
21
0
0
0
0
5
22
0
0
0
0
6
Section 5.3.1.2, “System Clock Control Register 1
23
0
0
0
0
7
Description
Section 14.3.5.2, “Interrupt Event Register
24
8
0
0
0
25
9
0
0
0
10
26
0
0
0
DMA_REV
11
27
0
0
0
Fast Ethernet Controller (FEC)
12
28
0
0
0
Access: User read/write
13
29
0
0
0
14
30
0
0
0
14-33
15
31
0
0
0