MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 672

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Power Management Control Module (PMC)
1
2
3
4
5
24-8
Sleep with DRAM running Set e300 SLEEP bit (HID0[10]
Core PLL change mode
PRE_DIV Copy
DRAM state during nap and sleep mode depends on setting of DDROFF bit in the PMC configuration register. When putting
DRAM interface in self-refresh mode during nap or sleep, no periphery-generated DRAM access is possible any more, and
DRAM transfer initiated by peripherals with master capability (DIU, USB, DMA, and FEC) is unable to take place. If DRAM is
left active, the transfer can continue while the core is in sleep mode.
To be increased with DRAM wakeup time if DRAM has been configured to self-refresh during nap or sleep mode.
DRAM state during pre-divider copy mode depends on setting of DDROFF bit in the PMC configuration register. In case DDR1
or DDR2 memory is used the user can set DDROFF bit so that DRAM goes to self-refresh state.
Plus DRAM wakeup time if DDROFF bit is set.
DRAM only goes to refresh state when core enters deep sleep mode if DRAM controller has been configured correctly. Please
refer to chapter on DRAM controller.
Sleep with DRAM in
Deep Sleep
Nap with DRAM in
DRAM running
Mode
Power mode
Deep sleep
self-refresh
self-refresh
Nap with
Doze
Suspended Running
Suspended Suspended Suspended Suspended Power-down Self-refresh
e300 state
Table 24-9. MPC5125 Power Modes – Sleep and Wake-Up Triggers
Events leading to entering this sleep mode
Set e300 DOZE bit (HID0[8]
— POW bit in MSR
Set e300 NAP bit (HID0[9]
— POW bit in MSR
v PMC_PMCCR
Set e300 NAP bit (HID0[9]
— POW bit in MSR
— PMC_PMCCR
— POW bit in MSR
— PMC_PMCCR
Set e300 SLEEP bit (HID0[10]
— POW bit in MSR
— PMC_PMCCR
Set e300 SLEEP bit (HID0[10]
— POW bit in MSR
— PMC_PMCCR
— POW bit in MSR
— PMC_PMCCR
Set e300 SLEEP bit (HID0[10]
Periphery
Table 24-8. MPC5125 Power Modes (continued)
clocks
MPC5125 Microcontroller Reference Manual, Rev. 2
3
3
3
3
3
3
= 00001
Suspended Suspended Active
= 00011
= 00001
= 00011
= 00100
= 01000
snooping
2
2
2
2
2
2
2
e300 bus
register is set
register is set
register is set
register is set
register is set
register is set
register is set
1
1
1
= 1) while
= 1) while
= 1)while
1
1
1
1
= 1) while
= 1) while
= 1) while
= 1) while
e300 time
registers
base
osc state
Interrupt to the e300 Power Architecture core
Decrementer interrupt
Any reset
Machine check exception
Interrupt to the e300 Power Architecture core
Decrementer interrupt
Any reset
Machine check exception
Interrupt to the e300 Power Architecture core
Decrementer interrupt
Any reset
Machine check exception
Interrupt to the e300 Power Architecture core
Any reset
Machine check exception
Interrupt to the e300 Power Architecture core
Any reset
Machine check exception
Asynchronous interrupt from GPIO, RTC, CAN
Power-on reset
Interrupt to e300 Power Architecture core
Reset
Machine check exception
PLL,
Events leading to return to full power
Depends
DRAM state
3,6
5
Freescale Semiconductor
13,200 IPS clk cycles
21,200 OSC clk cycles+
13,200 IPS clk cycle +
DRAM wakeup time
Wake-up time
4