MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 942

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.11.1.1 Asynchronous—Do-Start-Split
Do-Start-Split is the state that software must initialize a full- or low-speed asynchronous queue head. This
state is entered from the Do-Complete-Split state only after a complete-split transaction receives a valid
response from the transaction translator that is not a Nyet handshake.
For queue heads in this state, the host controller executes a start-split transaction to the transaction
translator. If the bus transaction completes without an error and PID code indicates an IN or OUT
transaction, then the host controller reloads the error counter (Cerr). If it is a successful bus transaction and
the PID Code indicates a SETUP, the host controller does not reload the error counter. If the transaction
translator responds with a NAK, the queue head is left in this state, and the host controller proceeds to the
next queue head in the asynchronous schedule.
If the host controller times out the transaction (no response, or bad response), the host controller
decrements Cerr and proceeds to the next queue head in the asynchronous schedule.
32.6.11.1.2 Asynchronous—Do-Complete-Split
This state is entered from the Do-Start-Split state only after a start-split transaction receives an ACK
handshake from the transaction translator.
For queue heads in this state, the host controller executes a complete-split transaction to the transaction
translator. If the transaction translator responds with a Nyet handshake, the queue head is left in this state,
the error counter is reset, and the host controller proceeds to the next queue head in the asynchronous
schedule. When a Nyet handshake is received for a bus transaction where the queue head's PID code
indicates an IN or OUT, the host controller reloads the error counter (Cerr). When a Nyet handshake is
received for a complete-split bus transaction where the queue head's PID Code indicates a SETUP, the host
controller must not adjust the value of Cerr.
Independent of PID code, the following responses have the indicated effects:
32-114
•
Transaction Error (XactErr). Timeout/data CRC failure. The error counter (Cerr) is decremented
by one and the complete split transaction is immediately retried (if possible). If there is not enough
time in the micro-frame to execute the retry, the host controller ensures that the next time the host
Error Count
Decrement
Figure 32-63. Host Controller Asynchronous Schedule Split-Transaction State Machine
Endpoint Halt
(CERR)
CERR goes
to Zero
XactErr
Endpoint Active
NaK
MPC5125 Microcontroller Reference Manual, Rev. 2
Start-
Split
Do
!XactErr
!NYET
.and.
.and.
!Stall
AcK
Complete-
Split
Do
Nyet
PidCode .eq. SETUP
XactErr
Endpoint Halt
Decrement Error Count
.and.
NaK
Set XactErr Bit and
Stall
(CERR)
Do Immediate Retry
of Complete-Split
Error Count
Decrement
Freescale Semiconductor
CERR goes
(CERR)
to Zero
and