MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 336

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Multi-port DRAM Controller Priority Manager
1
2
3
12-4
PRIOMAN_BASE
(0xFF40_9000)
0x014C–0x03FF Reserved
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Memory Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Offset from
0x011C
0x012C
0x013C
0x0110
0x0114
0x0118
0x0120
0x0124
0x0128
0x0130
0x0134
0x0138
0x0140
0x0144
0x0148
1
Granted Ack Counter 0 (GRANTED_ACK_CNTR0)
Granted Ack Counter 1 (GRANTED_ACK_CNTR1)
Granted Ack Counter 2( GRANTED_ACK_CNTR2)
Granted Ack Counter 3 (GRANTED_ACK_CNTR3)
Granted Ack Counter 4 (GRANTED_ACK_CNTR4)
Cumulative Wait Counter 0 (CUMULATIVE_WAIT_CNTR0)
Cumulative Wait Counter 1 (CUMULATIVE_WAIT_CNTR1)
Cumulative Wait Counter 2 (CUMULATIVE_WAIT_CNTR2)
Cumulative Wait Counter 3 (CUMULATIVE_WAIT_CNTR3)
Cumulative Wait Counter 4 (CUMULATIVE_WAIT_CNTR4)
Summed Priority Counter 0 (SUMMED_PRIORITY_CNTR0)
Summed Priority Counter 1 (SUMMED_PRIORITY_CNTR1)
Summed Priority Counter 2 (SUMMED_PRIORITY_CNTR2)
Summed Priority Counter 3 (SUMMED_PRIORITY_CNTR3)
Summed Priority Counter 4 (SUMMED_PRIORITY_CNTR4)
Table 12-1. PRIOMAN memory map (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Register
Chapter 2, “System Configuration and
Access
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
2
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Freescale Semiconductor
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