MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 321

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Freescale Semiconductor
DRAM_TIME_WTR1
DRAM_TIME_CCD_
Timing Parameter
For DRAMs that do not need this check, set equal to 4 × t
For DDR1 and Mobile-DDR t
For DDR1 and Mobile-DDR mode, t
This timing parameter controls precharge all command period duration. The equations shown are the JEDEC definition of the
t
Field is part of register 0x60, dram_extra_attributes
RPA
_OTHER
. Some DRAM vendors do not follow JEDEC on this, and list t
OTHER
DRAM_COMMAND
DRAM_ADDRESS
5
5
DRAM_DQS
DRAM_CLK
DRAM_DQ
Controls JEDEC
(JEDEC spec)
Parameter
CCD
—
Figure 11-7. Read to Precharge Timing Diagram
is 2 for 32-bit operation, 4 for 16-bit operation.
MPC5125 Microcontroller Reference Manual, Rev. 2
Bank A
READ
RTP
Table 11-9. Timing Parameters (continued)
is not explicitly given. It is equal to 4 for 16-bit mode, equal to 2 for 32-bit mode.
max(t
WL - RL + 2 + 2(32-bit mode)
WL - RL + 4 + 2(16-bit mode)
max(t
(All times in CSB clock
DRAM_TIME_RTP
dram_time_wtr1 =
CCD
dram_time_ccd =
CCD
NOP
,2) (32-bit mode) +1
Formulae
,4)(16-bit mode) +1
periods)
RRD
NOP
RPA
directly. In this case, set DRAM_TIME_RPA = t
PRECHG
Bank A
CAS to CAS delay from one chip select to the other
Because time is needed for data to be sent over,
this time is minimum 2 clocks in 32-bit mode, 4
clocks in 16-bit mode
dram_time_wtr1 is the write to read time for write
and read happening on different chip selects,
measured in clocks between write command and
read command. For this reason, WL (the write
latency) and the length of the actual write (2 or 4)
need to be added to t
Figure 11-9
D1
gives the details.
D2
Description
D3
WTR
.
D4
DRAM Controller
RPA
11-13
.