MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 544

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
1
2
3
4
21.2.1
21.2.1.1
The following registers are available:
21.2.1.1.1
1
2
21-4
Address: Base + 0x000
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Reset value is indeterminate.
The reset value is defined by the latched reset configuration word (RST_CONF). See
See bitfield description in
Reset
Reset —
•
•
•
•
•
•
•
•
•
W
W
R
R
Section 21.2.1.1.1, “Chip Select 0/Boot Configuration (LPC_CS0BOOTC) Register”
Section 21.2.1.1.2, “Chip Select[1:7] Configuration (LPC_CSnC) Registers”
Section 21.2.1.1.3, “Chip Select Control (LPC_CSC) Register”
Section 21.2.1.1.4, “Chip Select Status (LPC_CSS) Register”
Section 21.2.1.1.5, “Chip Select Burst Control (LPC_CSBC) Register”
Section 21.2.1.1.6, “Chip Select Deadcycle Control (LPC_CSDC) Register”
Section 21.2.1.1.7, “Chip Select Holdcycle Control (LPC_CSHC) Register”
Section 21.2.1.1.8, “Address Latch Timing (LPC_ALTR) Register”
Section 21.2.1.1.9, “TSIZ and TS Enable (LPC_TTE) Register”
MX
16
0
0
1,2
Register Descriptions
Chip Select/LPC Registers—0x0000
ALEV
Chip Select 0/Boot Configuration (LPC_CS0BOOTC) Register
17
Figure 21-2. Chip Select 0/Boot Configuration (LPC_CS0BOOTC) Register
0
0
1
AA
18
0
0
2
Table
CE
19
21-3.
0
1
3
WaitP
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
ALEN
21
0
0
5
—
22
0
6
1,2
DS
—
23
0
7
1,2
BM
24
0
0
8
ADD
—
RM
25
0
9
1,2
Chapter 2, “System Configuration and Memory
(0x024)
10
26
1
0
(0x020)
(0x038)
WTyp
Table
(0x034)
11
27
0
0
4-2.
WaitX
(0x008)
WS
12
28
0
0
Freescale Semiconductor
(0x030)
(0x02C)
Access: User read/write
(0x004–0x001C)
RS
13
29
0
0
(0x000)
WO
14
30
0
0
RO
15
31
0
1