MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 40

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration and Memory Map (XLBMEN + Mem Map)
The Internal Memory Map Registers’ Base Address register is shown in
2-6
0x0_0000–0_01FF
0x0_0200–0_08FF
0x0_0900–0_09FF
0x0_0A00–0_0AFF
0x0_0B00–0_0BFF
0x0_0C00–0_0CFF
0x0_0D00–0_0DFF
0x0_0E00–0_0EFF
0x0_0F00–0_0FFF
0x0_1000–0_10FF
Address: Base + 0x000
BASE_ADDR
(0xFF40_0000)
Reset
Reset
•
•
Offset from
IMMRBAR
Field
W
W
R
R
IMMRBAR should be updated during initial configuration of the device when only one host or
controller has access to the device
During system initialization, immediately after the release of reset, system software should set
IMMRBAR to the desired final location before enabling other I/O devices, which can become
potential bus masters. A copy of the IMMRBAR value should be written to Special Purpose
Register SPR311 (MBAR). Updating SPR311 is not automatic. When software changes
IMMRBAR, SPR311 should be updated by software at the same time. Otherwise, addresses of
configuration and data registers will be lost.
16
1
0
0
0
Figure 2-1. Internal Memory Map Registers’ Base Address Register (IMMRBAR)
Identifies the 12 most-significant address bits of the base of the 1 MB internal memory window.
17
1
0
0
1
Absolute offset
18
1
0
0
2
0xFF40_0C00
0xFF40_0D00
0xFF40_0A00
0xFF40_0B00
0xFF40_0E00
0xFF40_0F00
0xFF40_0000
0xFF40_0200
0xFF40_0900
0xFF40_1000
19
1
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 2-3. IMMRBAR field descriptions
20
4
1
0
0
1
Table 2-4. MPC5125 memory map
BASE_ADDR
System configuration (XLBMEN)
Reserved
Software watchdog timer (WDT)
Real time clock (RTC)
General purpose timer 1 (GPT1)
Integrated programmable interrupt controller (IPIC)
CSB arbiter
Reset module (RESET)
Clock module (CLOCK)
Power management control (PMC)
21
1
0
0
5
22
1
0
0
6
2
23
1
0
0
7
Description
Region Name
24
8
0
0
0
25
9
1
0
0
10
26
0
0
0
Figure
11
27
0
0
0
2-1.
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
Chapter 29/29-1
Chapter 27/27-1
Chapter 15/15-1
Chapter 18/18-1
Chapter 24/24-1
Section/Page
Chapter 2/2-1
Chapter 8/8-1
Chapter 4/4-1
Chapter 5/5-1
14
30
0
0
0
0
15
31
0
0
0
0