MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 446

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IIM/Fusebox
17.3.2.10 Divide Factor (IIM_DIVIDE) Register
The Divide Factor (IIM_DIVIDE) register contains the divide factor to generate a 32 kHz clock for
programming the fuses from the IPS clock. The unit of IPS clock is MHz.
Figure 17-10
17-10
PROTECTION_
Address: Base + 0x028
Address: Base + 0x03C
DIVIDE[7:0]
Reset
Reset
Reset
Reset
REG[7:0]
Field
Field
W
W
W
W
R
R
R
R
16
16
0
0
0
0
0
0
0
0
0
0
shows the bits in the IIM_DIVIDE register.
The fuses can be blown only when the value of this register is 0xAA. Any attempt to program the fuse while
the value is other than 0xAA is terminated with error, and the WPE bit is asserted.
This register provides a divide factor with which IPG_CLK can be divided to an 1 MHz clock. Then the 1 MHz
clock is divided to 32 kHz. Its value should be the frequency of IPS clock (unit: MHz), but the minimum is 1.
The default value is 0x42.
17
17
0
0
0
0
0
0
0
0
1
1
18
18
0
0
0
0
0
0
0
0
2
2
Figure 17-9. Program Protection (PRG_P) Register
Figure 17-10. Divide Factor (IIM_DIVIDE) Register
19
19
0
0
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 17-11. IIM_DIVIDE field descriptions
Table 17-10. PRG_P field descriptions
20
20
4
0
0
0
0
4
0
0
0
0
21
21
0
0
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
0
0
6
6
23
23
0
0
0
0
0
0
0
0
7
7
Description
Description
Table 17-11
24
24
8
0
0
0
8
0
0
0
25
25
9
0
0
0
9
0
0
1
describes the bit fields.
PROTECTION_REG[7:0]
10
26
10
26
0
0
0
0
0
0
DIVIDE[7:0]
11
27
11
27
0
0
0
0
0
0
Access: Supervisor read/write
Access: Supervisor read/write
12
28
12
28
0
0
0
0
0
0
Freescale Semiconductor
13
29
13
29
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
1
15
31
15
31
0
0
0
0
0
0