MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 730

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
If the receiver detect a valid data in time slot2, the SR[DATA_VALID] bit was set by the receiver. The
software can read the received data from the AC97Data register, synchronous the read access to this
register clears the SR[DATA_VALID] bit. If the receive detect an additional command data before the
previous data was read out, the SR[DATA_OVR] bit was also set to one. The previous received command
data word goes lost. A read access to the AC97Data register clears the SR[DATA_VALID] and
SR[DATA_OVR] register.
example, the AC97 controller only sends time slot 3 and slot4 data and expects data for time slot9, 10, 11,
and 12 on the receive site. For this purpose, the software must write two data words to the TxFIFO for one
complete AC97 frame and read four data words from the RxFIFO per frame.
25.5.4
Figure 25-54
testing the operation of a local PSC module channel by sending data to the transmitter and checking data
assembled by the receiver to ensure proper operations.
Features of this local loop-back mode are:
25.5.5
In remote loop-back mode, shown in
bit-by-bit on the TxD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing
25-52
AC97Slots
•
•
•
•
•
Register
SICR
IMR
CR
CR
Transmitter and CPU-to-receiver communications continue normally.
RxD input data is ignored.
TxD data is held marking.
The receiver is clocked by the transmitter clock.
Transmitter must be enabled, but the receiver need not be enabled.
Local Loop-Back Mode
Remote Loop-Back Mode
shows how TxD and RxD are internally connected in local loop-back mode. This mode is for
0x0301_0000
0x0300_000F
0xXXXX
Value
0x0A
0x05
Table 25-38. General Configuration Example AC97 Mode
CPU
Table 25-38
MPC5125 Microcontroller Reference Manual, Rev. 2
Disable the Tx and Rx part for configuration if the PSC was enabled by the work
before.
Select the enhanced AC97 mode
Define the expected receive and transmit slots
Select the desired interrupt
Enable Tx and Rx
Figure 25-54. Local Loop-Back
Figure
shows an example how to configure the AC97 controller. In this
25-55, the channel automatically transmits received data
Rx
Tx
Disabled
Disabled
Setting
RxD Input
TxD Input
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