MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 390

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
FEC FIFO/DMA registers requiring initialization are as follows:
14.4.1.1
In the fast Ethernet controller, the descriptor control RISC initializes some registers after ETHER_EN is
asserted. After the descriptor controller initialization sequence is complete, the hardware is ready for
operation.
The following describes the FEC RISC initialization operations.
14-34
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1. Initialize Backoff random number seed.
2. Activate receiver.
3. Activate transmit.
(ETH_X_WMRK) Register.”
(ETH_IADDR1) Register”
(ETH_IADDR2) Register.”
ETH_GADDR1/ETH_GADDR2. See
(ETH_GADDR1) Register”
(ETH_GADDR2) Register.”
ETH_PADDR1/ETH_PADDR2. See
Register”
ETH_OP_PAUSE (only needed for FDX flow control). See
Duration (ETH_OP_PAUSE) Register.”
ETH_R_CNTRL. See
ETH_X_CNTRL. See
ETH_MII_SPEED (optional). See
Register.”
Clear MIB_RAM (locations 0x0200–0x02E3).
Initialize ETH_R_FSTART (optional). See
(ETH_R_FSTART) Register.”
Initialize ETH_R_BUFF_SIZE. See
(ETH_R_BUFF_SIZE) Register.”
Initialize ETH_R_DES_START. See
(ETH_R_DES_START) Register.”
Initialize ETH_X_DES_START. See
(ETH_X_DES_START) Register.”
Initialize ETH_DMA_CONTROL. See
(ETH_DMA_CONTROL) Register.”
Initialize (empty) transmit descriptor ring
Initialize (empty) receive descriptor ring
ETH_X_WMRK (optional). See
ETH_IADDR2/ETH_IADDR1 (see
Descriptor Controller Initialization
and
Section 14.3.5.14, “Physical Address High (ETH_PADDR2) Register.”
MPC5125 Microcontroller Reference Manual, Rev. 2
Section 14.3.5.10, “Receive Control (ETH_R_CNTRL) Register.”
Section 14.3.5.12, “Transmit Control (ETH_X_CNTRL) Register.”
and
and
Section 14.3.5.17, “Descriptor Individual Address 2
Section 14.3.5.19, “Descriptor Group Address 2
Section 14.3.5.20, “FIFO Transmit FIFO Watermark
Section 14.3.5.8, “MII Speed Control (ETH_MII_SPEED)
Section 14.3.5.25, “Receive Buffer Size
Section 14.3.5.16, “Descriptor Individual Address 1
Section 14.3.5.13, “Physical Address Low (ETH_PADDR1)
Section 14.3.5.23, “Beginning of Receive Descriptor Ring
Section 14.3.5.24, “Beginning of Transmit Descriptor Ring
Section 14.3.5.18, “Descriptor Group Address 1
Section 14.3.5.26, “DMA Function Control
Section 14.3.5.22, “FIFO Receive Start
Section 14.3.5.15, “Opcode/Pause
Freescale Semiconductor