MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 325

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.2.5
The self-refresh command registers contain the commands sent to the DRAM when a self-refresh request
is given.
When the DRAM controller sees a low-to-high transition on the incoming self-refresh REQ signal coming
from the PMC controller, its reaction depends on the state of the internal self-refresh EN command bit.
Freescale Semiconductor
SELF_REFRESH_CMDn[15:0]
Address: Base + 0x0018 (SELF_REFRESH_CMD_0)
Reset
Reset
•
•
•
•
W
W
R
R
Write a command to DRAM without controlling the address. In this mode, it is possible to send
refresh, activate, and precharge commands to the DRAM
Write a DRAM mode register.
If the self-refresh EN bit is set, the DRAM controller writes self-refresh CMD[0:3] registers,
starting with reg 0 and ending with reg 3, to the compact command register. After the last register
has been written and its wait time has expired (if any), it pulls high the self-refresh ACK signal to
the PMC to acknowledge entry to self-refresh mode.
If the self-refresh EN bit is clear, the DRAM controller does not react to the request and keeps
self-refresh ACK signal low.
Base + 0x001C (SELF_REFRESH_CMD_1)
Base + 0x0020 (SELF_REFRESH_CMD_2)
Base + 0x0024 (SELF_REFRESH_CMD_3)
Figure 11-14
16
0
0
0
0
Field
Enter/Exit Self-Refresh Registers
Self-refresh REQ
Self-refresh ACK
17
0
0
0
1
gives the details.
18
0
0
0
2
Figure 11-14. Enter/exit Self-Refresh Command Protocol
Table 11-13. SELF_REFRESH_CMD_n field descriptions
19
Figure 11-13. Self-Refresh Command n Register
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
21
0
0
0
5
SELF_REFRESH_CMDn[15:0]
Base + 0x0028 (SELF_REFRESH_CMD_4)
Base + 0x002C (SELF_REFRESH_CMD_5)
Base + 0x0030 (SELF_REFRESH_CMD_6)
Base + 0x0034 (SELF_REFRESH_CMD_7)
22
0
0
0
6
23
0
0
0
7
24
8
0
0
0
Description
25
9
0
0
0
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Access: User read/write
13
29
0
0
0
DRAM Controller
14
30
0
0
0
11-17
15
31
0
0
0