MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 493

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
Part Number:
MPC5125YVN400
Manufacturer:
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Chapter 19
2
Inter-Integrated Circuit (I
C)
19.1
Overview
2
The Inter-Integrated Circuit (I
C) interface is a two-wire, bidirectional serial bus that provides a simple,
efficient method for data exchange among devices. The MPC5125 contains three identical and
independent I2C modules.
2
2
The I
C module operates up to a maximum bus load and timing of 400 kbit/s. Also, I
C modules are
capable of operating at higher baud rates, up to a maximum frequency equal to IPS_clock/20 with reduced
bus loading (where, the value 20 is the minimum SCL Divider in the block).
A maximum bus capacitance of 400 pF limits the maximum communication length and number of
possibly connected devices. The module can operate as fast as 400 kbit/s. This bus is suitable for
applications requiring occasional communications over a short distance among a number of devices. It also
provides flexibility, allowing more devices to be connected to the bus for further expansion and system
development.
2
I
C is a true multi-master bus including collision detection and arbitration to prevent data corruption if
two or more masters attempt to control the bus simultaneously. This feature provides the capability for
complex applications with multi-processor control. It may also be used for rapid testing and alignment of
end products via external connections to an assembly-line computer.
Figure 19-1
shows a block diagram
2
of the I
C module.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
19-1

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