MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 221

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 9
Direct Memory Access (DMA)
9.1
The direct memory access (DMA) module provides a flexible and efficient way to move blocks of data
within the system. The DMA controller reduces the workload on the microprocessor, allowing it to
continue execution of system software.
The DMA module includes a DMA engine, interfaces to peripheral buses and a dynamic clock gating
controller. The DMA engine performs source and destination address calculations, actual data movement
operations, and has a local memory containing the transfer control descriptors (TCD) for the channels. The
interfaces to peripheral buses grab data from source peripherals or pass data to destination peripherals. The
dynamic clock gating controller monitors the DMA engine and interface activities, turns off clocks to the
DMA engine, and DMA interfaces after detecting that the bus is idle.
9.1.1
The DMA module has the following features:
Freescale Semiconductor
•
•
•
•
Programmable multi-channel interface to peripherals
— Support for 64 channels with 32-bit data path widths
— Supports data movement of peripherals: MDDRC, PSC_FIFO, SDHC, LPC
Unrestricted data movement within physical memory address space
— All data movement via dual-address transfers: read from source, write to destination
— The transfer control descriptors (TCD) support these two-deep, nested transfer operations:
Support for external DMA request over GPIO interface
— 31 GPIO pins can be used as DMA requestors
Flexible protocol programmability
— Programmable source, destination addresses, and transfer size
— Transfer control descriptors (TCD) organized to support two-deep, nested transfer operations
— Support for fixed-priority and round-robin channel arbitration
— Channel completion reported via interrupt requests
— Support for scatter/gather DMA processing
Introduction
– Inner data transfer loop defined by a minor byte transfer count
– Outer data transfer loop defined by a major iteration count
Features
MPC5125 Microcontroller Reference Manual, Rev. 2
9-1