MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 902

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.5.6.2
The second and third doublewords of a queue head specify static information about the endpoint. This
information does not change over the lifetime of the endpoint. There are three types of information in this
region:
The host controller must not modify the bits in this region.
32-74
Packet Length
Maximum
•
•
•
31:28
26:16
Field
Field
Typ
2:1
RL
27
15
C
H
0
T
Endpoint Characteristics. These are the USB endpoint characteristics including addressing,
maximum packet size, and endpoint speed.
Endpoint Capabilities. These are adjustable parameters of the endpoint. They affect how the
endpoint data stream is managed by the host controller.
Split Transaction Characteristics. This data structure manages full- and low-speed data streams for
bulk, control, and interrupt via split transactions to USB2.0 hub transaction translator. There are
additional fields for addressing the hub and scheduling the protocol transactions (for periodic).
Endpoint Capabilities/Characteristics
This field indicates to the hardware whether the item referenced by the link pointer is an iTD, siTD or a QH. This
allows the host controller to perform the proper type of processing on the item after it is fetched.
00 iTD (isochronous transfer descriptor)
01 QH (queue head)
10 siTD (split transaction isochronous transfer descriptor)
11 FSTN (frame span traversal node)
Terminate.
1 Last QH (pointer is invalid).
0 Pointer is valid.
If the queue head is in the context of the periodic list, a one bit in this field indicates to the host controller that
this is the end of the periodic list. The host controller ignores this bit when the queue head is in the
asynchronous schedule. Software must ensure that queue heads reachable by the host controller always have
valid horizontal link pointers.
Nak Count Reload. This field contains a value used by the host controller to reload the Nak counter field.
Control Endpoint Flag. If the QH[EPS] field indicates the endpoint is not a high-speed device and the endpoint
is a control endpoint, software must set this bit to a one. Otherwise, it should always set this bit to a zero.
This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). The
maximum value this field may contain is 0x400 (1024).
Head of reclamation list flag. This bit is set by system software to mark a queue head as being the head of the
reclamation list.
Table 32-62. Endpoint Characteristics: Queue Head doubleword 1
Table 32-61. Queue Head doubleword 0 (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Description
Freescale Semiconductor