MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 102

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
1
2
5.2.1
Table 5-2
5-2
PSC clock generation sub-system is described in
MSCAN clock generation sub-system is described in
MSCAN_DIV
CORE_PLL
PSC_DIV
SYS_PLL
NFC_DIV
LPC_DIV
DIU_DIV
IPS_DIV
Domain
lists the reference clock for each peripheral.
Peripheral Clock Domains
1
2
Hardware Programmable
Hardware Programmable
Software Programmable
Software Programmable
Software Programmable
Software Programmable
Software Programmable
Software Programmable
GPIO1, GPIO2
FEC1, FEC2
Peripheral
PPC_PLL
CSBARB
PRIMAN
MDDRC
MSCAN
FIFOC
BDLC
FUSE
E300
MEM
DMA
EMB
PMC
NFC
IPIC
LPC
DIU
MPC5125 Microcontroller Reference Manual, Rev. 2
I2C
IIM
Table 5-1. Clock Domain Programming
Table 5-2. Peripheral Clock Reference
(Section 5.3.1, “Memory Map/Register
(Section 5.3.1, “Memory Map/Register
(Section 5.3.1, “Memory Map/Register
(Section 5.3.1, “Memory Map/Register
(Section 5.3.1, “Memory Map/Register
(Section 5.3.1, “Memory Map/Register
(Section 5.2.8.1, “System PLL Programming
(Section 5.2.8.2, “e300 Core PLL Programming
ips_clk
csb_clk
diu_clk, csb_clk, ips_clk
csb_clk
ppc_clk
csb_clk
ips_clk, lpc_clk, nfc_clk, csb_clk
ips_clk
ips_clk
ips_clk
ips_clk
ips_clk
ips_clk
ips_clk
lpc_clk
ddr_clk
csb_clk
ips_clk
nfc_clk, csb_clk
ips_clk, REF_CLK
csb_clk
Section 5.2.3, “PSC Clock Generation,” on page
Section 5.2.4, “MSCAN Clock Generation,” on page
1
Programming Interface
Reference Clock
Definition”)
Definition”)
Definition”)
Definition”)
Definition”)
Definition”)
Model”)
Model”)
5-3.
Freescale Semiconductor
5-4.