MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 381

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.3.5.14 Physical Address High (ETH_PADDR2) Register
The Physical Address High (ETH_PADDR2) register contains the upper 16 bits (bytes 4 and 5) of the
48-bit address used in the address recognition process to compare with the DA field of receive frames with
an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte source address field when
transmitting pause frames. Bits 16:31 of ETH_PADDR2 contain a constant-type field (0x8808) used for
transmission of pause frames. This register is not reset and bits 0:15 must be initialized.
14.3.5.15 Opcode/Pause Duration (ETH_OP_PAUSE) Register
The Opcode/Pause Duration (ETH_OP_PAUSE) register contains the 16-bit opcode and 16-bit pause
duration fields used in transmission of a pause frame. The OPCODE field is a constant value, 0x0001.
When another node detects a pause frame, that node pauses transmission for the duration specified in the
pause duration field. This register is not reset and must be initialized.
Freescale Semiconductor
Address: Base + 0x0E8
Reset
Reset
PADDR1
PADDR2
TYPE
Field
Field
W
W
R
R
—
16
1
0
This field comprises bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual
address to be used for exact match, and the source address field in pause frames.
This field comprises bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for an
exact match, and the source address field in pause frames.
This is the type field in pause frames. These 16 bits are a constant value of 0x8808.
—
17
0
1
Figure 14-15. Physical Address High (ETH_PADDR2) Register
—
18
0
2
—
19
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-18. ETH_PADDR1 field descriptions
Table 14-19. ETH_PADDR2 field descriptions
—
20
4
1
—
21
0
5
—
22
0
6
—
23
PADDR2
0
7
TYPE
Description
Description
—
24
8
0
—
25
9
0
—
10
26
0
—
11
27
0
Fast Ethernet Controller (FEC)
—
12
28
1
Access: User read/write
—
13
29
0
—
14
30
0
14-25
—
15
31
0