MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 91

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 4-2
1
2
Freescale Semiconductor
RST_CONF_SYSOSCEN
RST_CONF_ROM_LOC
RST_CONF_LPC_DBW
RST_CONF_COREPLL
Only valid when LPC boot mode is selected (ROM_LOC).
NFC memory access windows are placed at the location indicated by the BMS bit.
RST_CONF_SYSPLL
RST_CONF_LPC_TS
RST_CONF_SYSDIV
RST_CONF_LPCMX
RST_CONF_LPCWA
•
•
•
•
•
RST_CONF_BMS
Reset Parameter
MUX Flash mode
NOR Flash port size
Core PLL programming
System PLL programming
Clock divider
Reserved
Reserved
lists the parameters in the RST_CONF word and the pins associated with those parameters.
EMB_AD[14:12]
EMB_AD[11:8]
EMB_AD[1:0]
EMB_AD[7:5]
EMB_AD[4:3]
EMB_AD[18]
EMB_AD[15]
EMB_AD[16]
EMB_AD[17]
EMB_AD[19]
EMB_AD[22]
EMB_AD[2]
Signal
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 4-2. Reset Configuration Word
Boot mode select — Selects e300 boot vector
for LPC CS0 or NFC base address. See
Selects boot device.
00 LPC boot.
01 NAND (NFC) boot
10 Reserved.
11 Reserved.
LPC Data Port Size.
00 8-bit.
01 16- bit.
10 Reserved.
11 32-bit.
Core PLL Multiply factor.
See
options.
System PLL Multiply factor.
See
options.
Oscillator Bypass Mode.
0 System Oscillator bypass mode.
1 System Oscillator mode.
System PLL divider ratio.
See clock module for programming options.
Reserved. Must be connected to 1.
Reserved. Must be connected to 0.
LPC MUXED mode.
0 Non-muxed mode.
1 Muxed mode.
LPC Word/Byte address.
0 Address is interpreted as byte address.
1 Address is interpreted as word address.
Use LPC_TS, LPC_TSIZ0, LPC_TSIZ1 if boot from LPC.
0 Disable LPC_TS, LP_TSIZ0, LPC_TSIZ1 output if boot from LPC.
1 Enable LPC_TS, LPC_TSIZ0, LPC_TSIZ1 output if boot from LPC.
Section 5.2.8.2, “e300 Core PLL Programming Model,”
Section 5.2.8.1, “System PLL Programming Model,”
2
.
Description
Section 4.5.1, “BMS Operation.”
1
and configures default value
for programming
for programming
Reset
4-5