MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 701

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.4.1.14 Codec Clock Register (CCR)
This register defines the divider for the FrameSync and BCLK generation for codec mode. This register
value has effect only when the GenClk bit in the PSC control register SICR is set or the UART mode was
selected.
Freescale Semiconductor
Address: Base + 0x030
Reset
Reset
CTLR
Field
W
W
R
R
16
0
0
0
UART. Baud rate prescale value. The baud rate is calculated as:
The minimum CT value is 1; 0 denotes counter stop.
The prescaler was defined in the CSR register.
SPI. Delay After Transfer (DTL).
When the PSC is in SPI mode (SICR[SPI] = 1), the counter timer determine the length of time the PSC delays
after each serial transfer (the length of time that SS stays high/inactive between consecutive transfers). This
feature exists in a QSPI. Delay after transfer can be used to ensure the deselect time requirement (for
peripherals having such a requirement) is met. Some peripherals must be deselected for a minimum period
of time between consecutive serial transfers. A delay after transfer can be inserted between consecutive
transfers to a given peripheral to ensure its minimum deselect time requirement is met or to allow serial A/D
converters to complete conversion before the next transfer is made.
Other. Reserved.
17
0
0
Baud rate =
1
18
0
0
2
Figure 25-28. Codec Clock Register for Codec Mode (CCR)
FrameSyncDiv[0:7]
BCLKDiv[8:15]
19
0
0
3
CT[0:15] x prescaler
MPC5125 Microcontroller Reference Manual, Rev. 2
IPB clock frequency
Table 25-18. CTLR field descriptions
20
4
0
0
DTL =
21
0
0
5
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
IPB clock frequency
22
0
0
6
CT[0:15] + 2
23
0
0
7
Description
where:
CT[0:15] = {CTUR[0:7], CTLR[0:7]}
24
8
0
0
0
+
25
9
0
0
0
MCLK frequency
10
26
0
0
0
3
Programmable Serial Controller (PSC)
BCLKDiv[0:7]
11
27
0
0
0
12
28
0
0
0
Access: User read/write
13
29
0
0
0
14
30
0
0
0
25-23
15
31
1
0
0