MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 169

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.4.2.11.6
Any BDLC transmitting at the time a BREAK is detected treats the BREAK as if a transmission error had
occurred, and halt transmission.
If while receiving a message the BDLC module detects a BREAK symbol, it treats the BREAK as a
reception error.
If a BREAK symbol is received while the BDLC module is transmitting or receiving, the symbol invalid
or out of range flag in the BDLC_DLCBSVR register is set. Further transmission/reception is disabled
until the J1850 bus returns to the passive state and a valid EOF symbol is detected on the J1850 bus. If the
interrupt enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from the BDLC
module is generated. Reading the BDLC_DLCBSVR register clears this flag.
The BDLC module can transmit a BREAK symbol. It can receive a BREAK symbol from the J1850 bus.
6.4.2.12
The possible J1850 bus errors and the actions taken by the BDLC module are summarized in
6.4.3
The MUX Interface is responsible for bit encoding/decoding and digital noise filtering between the
Protocol Handler and the Physical Interface. Refer to
Freescale Semiconductor
Transmission Error
Cyclical Redundancy Check (CRC) Error CRC error flag set and interrupt generated if enabled.
Symbol Error
Framing Error
Bus short to V
Bus short to GND.
BREAK symbol reception
Error Condition
MUX Interface
DD
Bus Error Summary
.
Break
Table 6-22. BDLC Module J1850 Error Summary
MPC5125 Microcontroller Reference Manual, Rev. 2
BDLC module immediately ceases transmitting. Further transmission and reception
is disabled until a valid EOF symbol is detected. The symbol invalid or out of range
flag is set and interrupt generated if enabled.
The symbol invalid or out of range flag is set and interrupt generated if enabled.
Transmission and reception is disabled until a valid EOF symbol is detected.
The symbol invalid or out of range flag is set and interrupt generated if enabled.
Transmission and reception is disabled until a valid EOF symbol is detected.
The BDLC module does not transmit until short is corrected and a valid EOF is
detected. Depending upon when short occurs and is corrected, this error condition
may set the symbol invalid or out of range, CRC error, or loss of arbitration flags.
Short is seen as an idle bus by BDLC module. If a transmission attempt is made
before short is corrected, the symbol invalid or out of range flag is set and interrupt
generated if enabled. Another transmission can be initiated as soon as short is
corrected.
of range flag set and interrupt generated if enabled.Transmission and reception is
disabled until a valid EOF symbol is detected.
If doing so, the BDLC module immediately ceases transmitting. Symbol invalid or out
Figure
BDLC Module Function
6-1.
Byte Data Link Controller (BDLC)
Table
6-22.
6-33