MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 216

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSB Arbiter and Bus Monitor
8.3.2
The arbiter is responsible for tracking the following cases on the bus:
8.3.2.1
An address time out occurs if the address tenure was not ended before the specified time-out period
(programmed by ATR[ATO]) expires between the assertion of the TS signal until the assertion of the
AACK signal. In this case, the arbiter performs as follows:
8.3.2.2
A data time out occurs if the data tenure was not ended before the specified time-out period (programmed
by ATR[DTO]) expires between the assertion of DBB until the assertion of last TA. In this case, the arbiter
performs as follows:
8.3.2.3
The arbiter tracks the transfer error TEA signal that is asserted by one of the slaves. In this case, the arbiter
performs as follows:
8-16
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1. Ends the address tenure by asserting AACK.
2. Starts data tenure and ends it by asserting transfer error TEA.
3. Reports on the event to AER[ATO] if reporting is enabled by ATER[ATO].
4. Issues a reset request, an MCP, or a regular interrupt according to AERR[ATO] and AIDR[ATO]
5. Updates the transaction attributes and address of AEATR and AEADR for the first error event.
1. Ends the data tenure by asserting transfer error TEA.
2. Reports on this event in AER[DTO] if reporting is enabled by ATER[DTO].
3. Issues a reset request, an MCP, or a regular interrupt according to AERR[DTO] and AIDR[DTO],
4. Updates transaction attributes and address of AEATR and AEADR for the first error event.
1. Reports on the event to AER[ETEA] if reporting is enabled by ATER[ETEA].
2. Issues a reset request, an MCP, or a regular interrupt according to AERR[ETEA] and AIDR[ETEA]
3. Updates the transaction attributes and address of AEATR and AEADR for the first error event.
Address time out
Data time out
Transfer error External TEA
Address only transaction type
Reserved transaction type
Illegal (ECWIX/ECWOX) transaction type
if enabled by AMR[ATO] and if reporting is enabled by ATER[ATO].
if enabled by AMR[DTO] and if reporting is enabled by ATER[DTO].
if enabled by AMR[ETEA] and if reporting is enabled by ATER[ETEA].
Bus Error Detection
Address Time Out
Data Time Out
Transfer error External TEA
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor