MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 422

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Purpose Timers (GPT)
When using any mode of the GPT, unpredictable results can occur by arbitrarily switching from one mode
to another. Before re-configuring a timer channel to a different mode of operation, the timer channel should
be disabled by setting the TIMER_MS field in the GPT_MODE register to 0b000.
15.3.3
In this mode the I/O pin is an Output. When enabled the counters run until they reach the programmed
Terminal Count value. At this point, the specified output event is generated (toggle, pulse hi, or pulse low).
If enabled, a CPU interrupt is generated.
15.3.4
The OCT field of the GPT_MODE register for a particular Timer Channel is written to 0b00 to force its
associated Timer Channel Pin to a logic 0. No Output Compare event has to occur to force the Timer pin
to a logic 0.
15.3.5
A GPT Timer Channel can be programmed to issue a single pulse with positive polarity in response to an
Output Compare event. To enable this mode, the OCT field and the TIMER_MS field of the GPT_MODE
register must be programmed to 01 and 010, respectively. The High Time of the pulse, specified in
non-prescaled IP Bus clocks, is programmed into the OCPW field of the GPT_MODE register. To create
an Output Compare Event, write a value to the COUNT field of the GPT_COUNTER register that specifies
the time, expressed in prescaled IP Bus Clocks, when the next Output Compare event occurs. For example,
if the OCPW field is written to 3, the PRESCALE field is written to 2, and the Count field is written to 4,
the result is a positive pulse that is 3 IP Bus clocks wide that occurs 8 (Prescale = 2, Count = 4) IP Bus
clocks after writing the TIMER_MS field of the GPT_MODE register to 0b010. If the STOP_CONT bit
is set to 1 for continuous operation, the following wave form is generated.
15-12
Set Prescale = 2
Set Count = 4
Timer_MS = 010
OCT = 01
(8 IP Bus Clocks)
4 Prescaled IP
Output Compare
Force Output Low Immediately
Output Pulse High
Bus Clocks
It is the responsibility of the system software to set the Timer pin to the
desired state before setting up the PRESCALE and COUNT fields in the
GPT_COUNTER register.
3 Non-Prescaled
IP Bus Clocks
1st OC Event
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 15-5. Output Pulse High Time Example
(8 IP Bus Clocks)
4 Prescaled IP
Bus Clocks
3 Non-Prescaled
IP Bus Clocks
NOTE
2nd OC Event
(8 IP Bus Clocks)
4 Prescaled IP
Bus Clocks
3 Non-Prescaled
IP Bus Clocks
3rd OC Event
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