MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 1001

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.10 Deviations from the EHCI Specifications
The host mode operation of the modules is nearly EHCI-compatible with few minor differences. For the
most part, the modules conform to the data structures and operations described in Section 3, “Data
Structures,” and Section 4, “Operational Model,” in the EHCI specification. The particulars of the
deviations occur in these areas:
For the purposes of the USB controller implementing dual-role host/device controller with support for
OTG applications, it is necessary to deviate from the EHCI specification. Device operation and OTG
operation are not specified in the EHCI, and implementation supported in the OTG module is proprietary.
32.8.10.1 Device Operation
The co-existence of a device operational controller within the OTG module has little effect on EHCI
compatibility for host operation. However, because the OTG controller is initialized in neither host nor
device mode, the USB_USBMODE register must be programmed for host operation before the EHCI host
controller driver can begin EHCI host operations.
32.8.10.2 Non-Zero Fields in the Register File
Some of the reserved fields and reserved addresses in the capability registers and operational registers have
meaning in device mode; therefore, the following must be adhered to:
32.8.10.3 SOF Interrupt
The SOF interrupt is a free running 125 µsec interrupt for host mode. EHCI does not specify this interrupt,
but it has been added for convenience and as a potential software time base. The free running interrupt is
shared with the OTG-only device-mode start-of-frame interrupt. See
Freescale Semiconductor
USB Error Interrupt.
System Error
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Interrupt
Device operation (OTG module only)—In host mode, the device operational registers are generally
disabled and device mode is mostly transparent when in host mode. However, there are exceptions
documented in the following sections.
Embedded design interface—The modules do not have a PCI interface and therefore the PCI
configuration registers described in the EHCI specification are not applicable.
Write operations to all EHCI reserved fields (some of which are device fields in the OTG module)
in the operation registers should always be written to zero. This is an EHCI requirement of the
device controller driver that must be adhered to.
Read operations by the module must properly mask EHCI reserved fields (some of which are
device fields in the OTG module registers).
This error is redundant because it combines USB Interrupt and an error status in the dTD. The DCD
more aptly manages packet-level errors by checking dTD status field upon receipt of USB Interrupt
(w/ ENDPTCOMPLETE).
Unrecoverable error. Immediate Reset of core; free transfers buffers in progress and restart the DCD.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-101. Error Interrupt Events
Action
Universal Serial Bus Interface with On-The-Go
Section 32.2.4.2, “USB Status
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