MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 43

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The Power Architecture core may fetch its boot vector from a local bus peripheral device. For this purpose,
LPBAW[START_ADDR] and LPBAW[STOP_ADDR] reset values are set according to the value of the
BMS and ROM_LOC bits in the Reset Configuration Word High (RCWH) register.
Table 2-6
LPCSnAW registers.
2.2.5.1.4
The LocalPlus Access Window Registers (LPCSxAW) are shown in
Freescale Semiconductor
START_ADDR Any access on an address between Start and Stop Address enables the corresponding chip select. The
STOP_ADDR
Field
defines the reset values for the START_ADDR and STOP_ADDR bitfields in the LPBAW and
Table 2-6. LPBAW/LPCSnAW [START_ADDR] and [STOP_ADDR] Reset Values
BMS is bit 26 of the reset configuration word high register (RCWHR). Its
initial value is set by the state of the EMB_AD05 pin at the release of
PORESET. ROM_LOC is set by bits 22 and 21 of the reset configuration
word high register (RCWHR). The initial values of these bits are set by the
states of the EMB_AD0 and EMB_AD1 pins at the release of PORESET.
See
LocalPlus CS0–7 Access Window Registers (LPCSxAW)
START_ADDR is for the address comparison extended with 0x0000. The STOP_ADDR is for the address
comparison extended with 0xFFFF. This means the minimum address size is 64 KB. If the START_ADDR and
STOP_ADDR are set to 0xA000, the access window goes from 0xA000_0000 to 0xA000_FFFF.
Note: CS Boot and CS0 have the same physical CS pin.
Figure
ROM_LOC
01 or 1x
00
00
2-8.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 2-5. LPBAW field descriptions
BMS
0
1
x
START_ADDR
NOTE
Reset Value
0xFF80
0x0000
0x0100
Description
System Configuration and Memory Map (XLBMEN + Mem Map)
Figure
STOP_ADDR
Reset Value
0xFFFF
0x007F
0x0100
2-2.
2-9