MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 811

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

28.5.4
28.5.4.1
28.5.4.1.1
During block write, (CMD24–27) one or more blocks of data are transferred from the host to the card with
a CRC appended to the end of each block by the host. A card supporting block write can always accept a
block of data defined by WRITE_BL_LEN. If the CRC fails, the card indicates the failure on the DAT line
(see below); the transferred data is discarded and not written, and all further transmitted blocks (in multiple
block write mode) are ignored.
If the host uses partial blocks with accumulated length not block aligned and block misalignment is not
allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card shall detect the block
misalignment error and abort programming before the beginning of the first misaligned block. The card
sets the ADDRESS_ERROR error bit in the status register, and while ignoring all further data transfer,
waits in the receive-data-state for a stop command. The write operation is also aborted if the host tries to
write over a write protected area. In this case, however, the card sets the WP_VIOLATION bit.
Programming of the CID and CSD registers does not require a previous block length setting. The
transferred data is also CRC protected. If a part of the CSD or CID register is stored in ROM, this
unchangeable part must match the corresponding part of the receive buffer. If this match fails, the card
reports an error and does not change any register contents. Some cards may require unpredictable times to
write a block of data. After receiving a block of data and completing the CRC check, the card begins
Freescale Semiconductor
card_registry()
{
while (ResponseTO from STATUS){
if(card==combo or sdio)
{
send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x01, 0x40);
response
rca = SDIO_RCA = address from response FIFO;
}
else if(card==sd)
{
send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x02, 0x40);
send_cmd_wait_resp(SET_RELATIVE_ADDR, 0x00, 0x01, 0x40); //card publish the RCA in
response
rca = SD_RCA = address from response FIFO;
}
else if(card==mmc)
{
send_cmd_wait_resp(ALL_SEND_CID, 0x00, 0x00, 0x02, 0x40);
rca = MMC_RCA = 0x1;
send_cmd_wait_resp(SET_RELATIVE_ADDR, MMC_RCA_arguement, 0x01, 0x40);
}
else
exit due to card not identified;
}
send_cmd_wait_resp(SELECT_CARD, RCA_arguement, 0x41, 0x40);
}
Card Access
Block Access — Block Write & Block Read
Block Write
MPC5125 Microcontroller Reference Manual, Rev. 2
//card publish the RCA in
Secure Digital Host Controller (SDHC)
28-39