MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 821

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

29.3
29.3.1
To manage a case in which the software becomes trapped in a loop with no controlled exit, the MPC5125
platform provides the WDT option to prevent system lock. Watchdog timer operations are configured in
the Software Watchdog Control Register (WDT_SWCRR).
By default, the WDT is enabled after reset to cause a hardware reset or non-maskable MCP interrupt if the
WDT decrements to 0x0000. If the WDT is not needed, the user must clear the WDT_SWCRR[SWEN]
bit to disable it. If used, the WDT requires a special service sequence to be executed periodically. Without
this periodic servicing, it times out and issues a reset or a nonmaskable MCP interrupt, as programmed in
WDT_SWCRR[SWRI]. After software writes to the SWRI bit, the state of SWEN cannot be changed.
The WDT service sequence consists of the following two steps:
This special service sequence reloads the WDT, and the timing process begins again. If a value other than
0x556C or 0xAA39 is written to the WDT_SWSRR, the entire sequence must start over. Although the
writes must occur in the correct order before a timeout, any number of instructions can be executed
between the writes. This allows interrupts and exceptions to occur between the two writes when necessary.
Figure 29-4
Freescale Semiconductor
1. Write 0x556C to WDT_SWSRR.
2. Write 0xAA39 to WDT_SWSRR.
Field
WS
Functional Description
Software Watchdog Timer Unit
shows a state diagram for the WDT.
Software watchdog service. The user must write 0x556C followed by 0xAA39 to this register to prevent WDT
timeout. WDT_SWSRR[WS] can be written at any time, but returns all zeros when read.
Not 0x556C/
Do not reload
Reset
Figure 29-4. Software Watchdog Timer Service State Diagram
Waiting for 0x556C
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 29-4. WDT_SWSRR field descriptions
State 0
Not 0xAA39/Do not reload
0x556C/Do not reload
0xAA39/Reload
Description
Waiting for 0xAA39
State 1
Software Watchdog Timer (WDT)
29-5