MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 604

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MSCAN
Receive buffer start with base address 0x40, Transmit buffer start with base address 0x60
To simplify the programmer interface, the receive and transmit message buffers have the same outline.
Each message buffer allocates 16 bytes in the memory map containing a 13-byte data structure.
An additional transmit buffer priority register (TBPR) is defined for the transmit buffers. Within the last
two bytes of this memory map, the MSCAN stores a special 16-bit time stamp, which is sampled from an
internal timer after successful transmission or reception of a message. This feature is only available for
transmit and receiver buffers, if the TIME bit is set (see
(CANCTL0)”).
The time stamp register is written by the MSCAN. The Power Architecture can only read these registers.
Figure 22-20
identifiers. The mapping of standard identifiers into the IDR registers is shown in
All bits of the receive and transmit buffers are of indeterminate value out of reset because of RAM-based
implementation
indeterminate value.
1. Exception: The transmit priority registers are 0 out of reset.
22-26
shows the common 13-byte data structure of receive and transmit buffers for extended
1
. All reserved or unused bits of the receive and transmit buffers always read an
1
2
Base + 0x40 + offset (RX)
Base + 0x60 + offset (TX)
Not applicable for receive buffers.
Read-only.
Offset Address
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 22-21. Message Buffer Organization
0x0C
0x0D
0x1C
0x1D
0x00
0x01
0x04
0x05
0x08
0x09
0x10
0x11
0x14
0x15
0x18
0x19
Identifier Register 0
Identifier Register 1
Identifier Register 2
Identifier Register 3
Data Segment Register 0
Data Segment Register 1
Data Segment Register 2
Data Segment Register 3
Data Segment Register 4
Data Segment Register 5
Data Segment Register 6
Data Segment Register 7
Data Length Register
Transmit Buffer Priority Register
Time Stamp Register (High Byte)
Time Stamp Register (Low Byte)
Section 22.3.2.1, “MSCAN Control 0 Register
Register
1
2
2
Figure
Freescale Semiconductor
22-21.