MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 786

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.3.2.7
The SDHC Block Length (SDHC_BLK_LEN) register defines the number of bytes in a block. Because
the stream mode of MMC is not supported, block length must be set for every transfer. Block lengths
supported by the SDHC range from 1 to 2048 bytes, but the block size supported by the card must be
checked before configuring this register. For SDIO, the block length must be less than the maximum block
size defined in the card’s CCCR. For SD/MMC, the block length must be less than the maximum block
size defined in the card’s CSD register.
Figure 28-8
28-14
Address: Base + 0x18
Reset
Reset
W
W
R
R
16
0
0
0
0
0
shows the SDHC_BLK_LEN register and
SDHC Block Length (SDHC_BLK_LEN) Register
Software should write to this register only when no SD bus transaction is
executing.
17
0
0
0
0
1
18
Figure 28-8. SDHC Block Length (SDHC_BLK_LEN) Register
0
0
0
0
2
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
0
21
0
0
0
5
22
0
0
0
6
NOTE
23
0
0
0
7
Table 28-10
24
8
0
0
0
BLOCK LENGTH
25
9
0
0
0
describes the bit fields.
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0