MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 943

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

If the PID code indicates an IN, then any of following responses are expected:
If the PID code indicates an OUT/SETUP, any of following responses are expected:
32.6.11.2 Split Transaction Interrupt
Split-transaction interrupt-IN/OUT endpoints are managed using the same data structures used for
high-speed interrupt endpoints. They both co-exist in the periodic schedule. Queue heads/qTDs offer the
set of features required for reliable data delivery, which is characteristic to interrupt transfer types. The
split-transaction protocol is managed completely within this defined functional transfer framework. For
example, the host controller visits a queue head, executes a high-speed transaction (if criteria are met), and
advances the transfer state (or not) depending on the results of the entire transaction for a high-speed
endpoint. For low- and full-speed endpoints, the details of the execution phase are different (that is, takes
more than one bus transaction to complete), but the remainder of the operational framework is intact.
Freescale Semiconductor
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controller begins executing from the asynchronous schedule, it must begin executing from this
queue head. If another start-split (for some other endpoint) is sent to the transaction translator
before the complete-split is really completed, the transaction translator could dump the results
(which were never delivered to the host). This is why the core specification states the retries must
be immediate. When the host controller returns to the asynchronous schedule in the next
micro-frame, the first transaction from the schedule is the retry for this endpoint. If Cerr went to
zero, the host controller halts the queue.
NAK. The target endpoint Nak'd the full- or low-speed transaction. The state of the transfer is not
advanced and the state is exited. If the PID Code is a SETUP, then the Nak response is a protocol
error. The XactErr status bit is set and the Cerr field is decremented.
STALL. The target endpoint responded with a STALL handshake. The host controller sets the halt
bit in the status byte and retires the qTD, but does not attempt to advance the queue.
DATA0/1. On reception of data, the host controller ensures the PID matches the expected data
toggle and checks CRC. If the packet is good, the host controller advances the state of the transfer
(for example, moves the data pointer by the number of bytes received, decrements the
BytesToTransfer field by the number of bytes received, and toggles the dt bit). The host controller
then exits this state. The response and advancement of transfer may trigger other processing events,
such as retirement of the qTD and advancement of the queue.
If the data sequence PID does not match the expected, the data is ignored, the transfer state is not
advanced, and this state is exited.
ACK. The target endpoint accepted the data, so the host controller must advance the state of the
transfer. The current offset field is incremented by maximum packet length or bytes to transfer,
whichever is less. The bytes to transfer field is decremented by the same amount and the data toggle
bit (dt) is toggled. The host controller then exits this state.
Advancing the transfer state may cause other processing events such as retirement of the qTD and
advancement of the queue.
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-115