MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 972

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
Serial Bus Babble
When a device transmits more data on the USB than the host controller is expecting for this transaction, it
is defined to be babbling. In general, this is called a packet babble. When a device sends more data than
the maximum length number of bytes, the host controller sets the babble detected bit to 1 and halts the
endpoint if it is using a queue head. Maximum length is defined as the minimum of total bytes to transfer
and maximum packet size. The Cerr field is not decremented for a packet babble condition (only applies
to queue heads). A babble condition also exists if IN transaction is in progress at high-speed EOF2 point.
This is called a frame babble. A frame babble condition is recorded into the appropriate schedule data
structure. In addition, the host controller must disable the port to which the frame babble is detected.
The USBERRINT bit in the USB_USBSTS register is set. If the USB error interrupt enable bit in the
USB_USBINTR register is set, a hardware interrupt is signaled to the system at the next interrupt
threshold. The host controller must never start an OUT transaction that babbles across a micro-frame EOF.
When a host controller detects a data PID mismatch, it must disable the packet babble checking for the
duration of the bus transaction or do packet babble checking based solely on maximum packet size. The
USB core specification defines the requirements on a data receiver when it receives a data PID mismatch
(for example, expects a DATA0 and gets a DATA1 or visa-versa). In summary, it must ignore the received
data and respond with an ACK handshake to advance the transmitter's data sequence.The EHCI interface
allows system software to provide buffers for a control, bulk, or interrupt IN endpoint that are not an even
multiple of the maximum packet size specified by the device. When a device misses an ACK for an IN
endpoint, the host and device are out of synchronization with respect to the progress of the data transfer.
The host controller may have advanced the transfer to a buffer that is less than maximum packet size. The
device re-sends its maximum packet size data packet, with the original data PID, in response to the next
IN token. To properly manage the bus protocol, the host controller must disable the packet babble check
when it observes the data PID mismatch.
Data Buffer Error
This event indicates that either an overrun of incoming data or an underrun of outgoing data has occurred
for this transaction. This would generally be caused by the host controller not being able to access required
data buffers in memory within necessary latency requirements. These conditions are not considered
transaction errors and do not affect the error count in the queue head. When these errors do occur, the host
controller records the fact the error occurred by setting the data buffer error bit in the queue head, iTD or
siTD.
If the data buffer error occurs on a non-isochronous IN, the host controller does not issue a handshake to
the endpoint. This forces the endpoint to resend the same data (and data toggle) in response to the next IN
to the endpoint.
If the data buffer error occurs on an OUT, the host controller must corrupt the end of the packet so that it
cannot be interpreted by the device as a good data packet. Simply truncating the packet is not considered
acceptable. An acceptable implementation option is to one's complement the CRC bytes and send them.
32-144
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EPS field indicates a high-speed device and it returns a Nak handshake to a SETUP.
EPS field indicates a high-speed device and it returns a Nyet handshake to a SETUP.
EPS field indicates a low- or full-speed device and the complete-split receives a Nak handshake.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor