MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 748

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PSC Centralized FIFO Controller (FIFOC)
26.2.1.13 FIFOC Debug Register (FIFOC_DEBUG)
26.3
During the functional mode, the FIFOC controller provides the data for all PSC transmitters and stores the
data from all PSC receiver. If the FIFO gets a request from the PSC, the required data from the TX FIFO
memory is written to the PSC transmit register or the received data is read from the RX register and is
stored in the RX FIFO area. If the number of data inside the FIFO register reaches the programmed alarm
level, the enabled request lines are asserted to inform the system that the RX data is available or new TX
data is required.
26-14
Address: FIFOC Base + 0x10
Reset
Reset
DEBUG
LOCK
Field
W
W
R
R
Functional Description
16
0
0
0
0
0
Debug Mode
0 Normal Operation Mode
1 Debug mode. The Interrupt status register and the pointer register are writeable. The debug bit is only
State Machine Lock
0 Normal operation mode
1 Lock the internal machine control state machine. All PSC requests are ignored. Only access from the IP
17
0
0
0
0
1
writeable with a 32-bit access to this register during bit[31:16] containing 0x8442.
Bus interface is possible.The lock bit is only writeable with a 32-bit access to this register during bit[31:16]
containing 0x8442.
18
0
0
0
0
2
Figure 26-14. FIFOC Debug Register (FIFOC_DEBUG)
19
0
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 26-16. FIFOC_DEBUG field descriptions
20
4
0
0
0
0
21
0
0
0
0
5
22
0
0
0
0
6
23
0
0
0
0
7
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
11
27
0
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
LOCK
14
30
0
0
0
BUG
DE
15
31
0
0
0