MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 554

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21.2.1.2.1
21-14
Address: Base + 0x100
PACKET SIZE This 31-bit field represents the number of bytes SCLPC must transact before going idle and waiting for a
Reset
Reset
RESTART
•
•
•
•
•
Field
W
W
R
R
Section 21.2.1.2.4, “SCLPC Enable (LPC_SCLPC_E) Register”
Section 21.2.1.2.5, “SCLPC Status (LPC_SCLPC_S) Register”
Section 21.2.1.2.6, “SCLPC Bytes Done (LPC_SCLPC_BD) Register”
Section 21.2.1.2.7, “EMB Share and Wait Count (LPC_EMB_SC) Register”
Section 21.2.1.2.8, “EMB Pause Control (LPC_EMB_PC) Register”
START
RE
16
0
0
0
0
SCLPC Packet Size (LPC_SCLPC_PS) Register
Writing a 1 to this bit begins a SCLPC transfer. It clears automatically and always reads back as 0.
Note: Start transfers after LPC FIFO and SCLPC are configured.
restart.
Note: The co-location of the restart bit and the packet_size field allows software to restart a transaction and
Note: PACKET SIZE needs to be either a multiple of BPT setting (see
17
0
0
1
change the packet_size in a single write. Maximum packet size is 2 GB – 1 bytes.
Figure 21-11. SCLPC Packet Size (LPC_SCLPC_PS) Register
18
0
0
2
19
0
0
3
Table 21-12. LPC_SCLPC_PS field descriptions
MPC5125 Microcontroller Reference Manual, Rev. 2
20
4
0
0
21
0
0
5
22
0
0
6
PACKET SIZE
23
0
0
7
PACKET SIZE
Description
24
8
0
0
25
9
0
0
10
26
0
0
(0x0114)
(0x010C)
Table
(0x0120)
11
27
0
0
21-15) or of 8.
(0x0118)
12
28
0
0
Freescale Semiconductor
(0x011C)
Access: User read/write
13
29
0
0
14
30
0
0
15
31
0
0