MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 326

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DRAM Controller
When the DRAM controller sees a high-to-low transition on the incoming self-refresh REQ signal coming
from the PMC controller, its reaction is similar and depends on the state of the internal self-refresh EN
command bit again.
11.3.2.6
11.3.2.7
11-18
DQS_SLAVE_[3:0]_
Address: Base + 0x0038
Address: Base + 0x003C
OFFSET_COUNT
Reset
Reset
Reset
Reset
•
•
W
W
W
W
R
R
Field
R
R
If the self-refresh EN bit is set, the DRAM controller writes self-refresh CMD[4:7] registers,
starting with register CMD4 and ending with register CMD7, to the compact command register.
After the last register has been written and its wait time has expired (if any), it pulls low the
self-refresh ACK signal to the PMC to acknowledge exit from self-refresh mode.
If the self-refresh EN bit is clear, the DRAM controller does not react to the request and keeps
self-refresh ACK signal high.
16
16
0
0
0
0
0
0
0
0
0
0
Figure 11-15. DQS Config Offset Count (DQS_CONFIG_OFFSET_COUNT) Register
DQS Config Offset Count (DQS_CONFIG_OFFSET_COUNT) Register
DQS Config Offset Time (DQS_CONFIG_OFFSET_TIME) Register
Figure 11-16. DQS Config Offset Time (DQS_CONFIG_OFFSET_TIME) Register
17
17
0
0
0
0
0
0
1
1
There is a separate field for each DQS input to the controller. These fields code for an offset counted in
elemental gate delay increments applied to each DQS slave. The number is a two-complement number
that can be positive and negative.
This register can be used to compensate systematic delay shift in the DRAM controller due to processing.
Leave this register all-zero, unless Freescale issues a report giving a different value.
DQS SLAVE 3 OFFSET COUNT[6:0]
DQS SLAVE 1 OFFSET COUNT[6:0]
Table 11-14. DQS_CONFIG_OFFSET_COUNT field descriptions
18
18
0
0
0
0
0
0
2
2
DQS SLAVE 3 OFFSET TIME[4:0]
DQS SLAVE 1 OFFSET TIME[4:0]
19
19
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
4
0
0
21
21
0
0
0
0
5
5
22
22
0
0
0
0
6
6
23
23
0
0
0
0
7
7
Description
24
24
8
0
0
0
0
8
0
0
0
0
25
25
9
0
0
9
0
0
0
0
DQS SLAVE 2 OFFSET COUNT[6:0]
DQS SLAVE 0 OFFSET COUNT[6:0]
10
26
10
26
0
0
0
0
0
0
DQS SLAVE 2 OFFSET TIME[4:0]
DQS SLAVE 0 OFFSET TIME[4:0]
11
27
11
27
0
0
0
0
12
28
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
14
30
14
30
0
0
0
0
15
31
15
31
0
0
0
0