MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 362

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3
14.3.1
There are two FECs (FEC1, FEC2) in the MPC5125. Each FEC is programmed by a combination of
control/status registers (CSRs) and buffer descriptors. The CSRs are used for mode control, interrupts, and
to extract status information. The descriptors are used to pass data buffers and related buffer or frame
information between the hardware and software.
All accesses to and from the registers must be via 32-bit accesses. There is no support for accesses other
than 32-bit.
This section defines the memory map and the registers, and then defines the buffer descriptors.
14.3.2
bytes each. The first is used for control/status registers. The second contains event/statistic counters held
in the MIB block.
14-6
Each FEC implementation requires a 1 KB memory map space that is divided into two sections of 512
FECn_RXD[3:2]
FECn_TX_CLK/
RMII_REF_CLK
FECn_TXD[3:2]
FECn_RX_ER/
FECn_RXD_1/
FECn_RXD_0/
FECn_TX_EN/
FECn_TXD_1/
FECn_TXD_0/
FECn_TX_ER
Signal Name
RMII_RX_ER
RMII_TX_EN
RMII_RX1
RMII_RX0
RMII_TX1
RMII_TX0
Memory Map and Register Definition
Overview
Top-Level Module Memory Map
Table 14-2
MII
X
X
X
X
X
X
X
X
X
X
7-wire
—
—
—
—
—
—
Table 14-1. FEC signal Descriptions (continued)
X
X
X
X
defines the top-level memory map for each FEC.
MPC5125 Microcontroller Reference Manual, Rev. 2
RMII
—
—
—
X
X
X
X
X
X
X
I/O
O
O
O
O
O
I
I
I
I
I
Asserted—These signals contain the Ethernet input data
transferred from PHY to the MAC when FECn_RX_DV is asserted.
Asserted—This signal contains the Ethernet input data transferred
from PHY to the MAC when FECn_RX_DV is asserted.
Asserted—This signal contains the Ethernet input data transferred
from PHY to the MAC when FECn_RX_DV is asserted.
Asserted—When asserted with FECn_RX_DV, the PHY has
detected an error in the current frame. When FECn_RX_DV is not
asserted, RX_ER has no effect.
Asserted—A continuous clock that provides a timing reference for
FECn_TX_EN, FECn_TXD, and FECn_TX_ER. In RMII mode, this
signal is the reference clock for receive, transmit, and the control
interface.
Asserted— These signals contain the serial output Ethernet data
and valid only during assertion of FECn_TX_EN
Asserted— This signal contains the serial output Ethernet data
and valid only during assertion of FECn_TX_EN
Asserted— This signal contains the serial output Ethernet data
and valid only during assertion of FECn_TX_EN
Asserted—Assertion of this signal indicates there are valid nibbles
being presented on the MII. This signal is asserted with the first
nibble of the preamble and is negated prior to the first
FECn_TX_CLK following the final nibble of the frame.
Asserted—Assertion of this signal for one or more clock cycles
while FECn_TX_EN is also asserted, PHY sends one or more
illegal symbols. FECn_TX_ER has no effect when operating at
10 Mbit/s or when FECn_TX_EN is deasserted.
Description
Freescale Semiconductor