MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 987

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

should enable the stall bits (both directions) as a pair. A single write to the USB_ENDPTCTRLn register
can ensure both stall bits are set at the same instant.
32.8.4.3
Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe.
For more information on data toggle, refer to the USB 2.0 specification.
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a '1' to the data toggle reset bit in the USB_ENDPTCTRLn register. This should only
be necessary when configuring/initializing an endpoint or returning from a STALL condition.
Data Toggle Inhibit is for test purposes only and should never be used during normal device controller
operation.
Setting the data toggle inhibit bit active (1) causes the USB controller to ignore the data toggle pattern
normally sent and accept all incoming data packets regardless of the data toggle state.
In normal operation, the USB controller checks the DATA0/DATA1 bit against the data toggle to determine
if the packet is valid. If data PID does not match the data toggle state bit maintained by the device
controller for that endpoint, the data toggle is considered not valid. If the data toggle is not valid, the device
controller assumes the packet was already received and discards the packet (not reporting it to the DCD).
To prevent the USB controller from re-sending the same packet, the device controller responds to the error
packet by acknowledging it with either an ACK or NYET response.
32.8.5
All transactions on the USB bus are initiated by the host and the device must respond to any request from
the host within the turnaround time stated in the USB 2.0 Specification.
A USB host sends requests to the device controller (USB controller) in an order that cannot be precisely
predicted as a single pipeline, so it is not possible to prepare a single packet for the device controller to
execute. However, the order of packet requests is predictable when the endpoint number and direction is
Freescale Semiconductor
SETUP packet received by a non-control endpoint.
IN/OUT/PING packet received by a non-control endpoint.
IN/OUT/PING packet received by a non-control endpoint.
SETUP packet received by a control endpoint.
IN/OUT/PING packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint.
Device Operational Model For Packet Transfers
Data Toggle
Any write to the USB_ENDPTCTRLn register during operational mode
must preserve the endpoint type field (i.e., perform a read-modify-write).
USB Packet
Table 32-91. Device Controller Stall Response Matrix
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Endpoint Stall Bit
N/A
N/A
1
0
1
0
Universal Serial Bus Interface with On-The-Go
Effect on STALL bit
Cleared
None
None
None
None
None
ACK/NAK/NYET
ACK/NAK/NYET
USB Response
STALL
STALL
STALL
ACK
32-159