MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 909

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.2.1
Port Suspend/Resume
System software places the USB into suspend mode by writing a one into the appropriate USB_PORTSCn
suspend bit. Software must only set the suspend bit when the port is in the enabled state (port enabled bit
is a one).
The host controller may evaluate the suspend bit immediately or wait until a micro-frame or frame
boundary occurs. If evaluated immediately, the port is not suspended until the current transaction (if one
is executing) completes. Therefore, there may be several micro-frames of activity on the port until the host
controller evaluates the suspend bit. The host controller must evaluate the suspend bit at least every frame
boundary.
System software can initiate a resume on the suspended port by writing a one to the force port resume bit.
Software should not attempt to resume a port unless the port reports that it is in the suspended state. If
system software sets the force port resume bit when the port is not in the suspended state, the resulting
behavior is undefined. To assure proper USB device operation, software must wait for at least 10
milliseconds after a port indicates it is suspended (suspend bit is a one) before initiating a port resume via
the force port resume bit. When force port resume bit is set, the host controller sends resume signaling
down the port. System software times the duration of the resume (nominally 20 milliseconds), and then
clears the force port resume bit. When the host controller receives the write to transition force port resume
to zero, it completes the resume sequence as defined in the USB specification, and clears both the force
port resume and suspend bits. Software-initiated port resumes do not affect the port change detect bit in
the USB_USBSTS register nor do they cause an interrupt if the port change interrupt enable bit in the
USB_USBINTR register is a one. When a wake event occurs on a suspended port, the resume signaling is
detected by the port and the resume is reflected downstream within 100 µsec. The port's force port resume
bit is set and the port change detect bit in the USB_USBSTS register is set. If the port change interrupt
enable bit in the USB_USBINTR register is a one, the host controller issues a hardware interrupt.
System software observes the resume event on the port, delays a port resume time (nominally 20
milliseconds), and then terminates the resume sequence by clearing the force port resume bit in the port.
The host controller receives the write of zero to force port resume, terminates the resume sequence, and
clears the force port resume and suspend port bits. Software can determine the port is enabled (not
suspended) by sampling the USB_PORTSCn register and observing that the suspend and force port resume
bits are zero. Software must ensure that the host controller is running (HCHalted bit in the USB_USBSTS
register is a zero), before terminating a resume by clearing the port's force port Resume bit. If HCHalted
is a one when force port resume is cleared, SOFs does not occur down the enabled port and the device
returns to suspend mode in a maximum of 10 milliseconds.
Table 32-69
summarizes the wake-up events. When a resume event is detected, the port change detect bit
in the USB_USBSTS register is set. If the port change interrupt enable bit is a one in the USB_USBINTR
register, the host controller also generates an interrupt on the resume event. Software acknowledges the
resume event interrupt by clearing the port change detect status bit in the USB_USBSTS register.
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
32-81