MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 671

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

24.3
Based on the four power modes of the embedded low-power e300 Power Architecture CPU core, the
module provides five power modes: full-power, doze, nap, sleep, and deep sleep mode. Special sleep
modes are provided to allow core PLL reprogramming and pre-divider ratio adjustment. They are called
core PLL change mode and pre-divider copy mode. A reference to what is running and what is disabled in
the various modes is given in
in
Freescale Semiconductor
Core PLL Change Suspended Running
Table
Full Power
WSP6
WSP5
WSP4
WSP3
WSP2
WSP1
WSP0
Field
Mode
Sleep
Doze
Nap
24-9.
Functional Description
Deep sleep wake up signal polarity select 6. RTC.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 5. MSCAN1_RX.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 4. MSCAN2_RX.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 3. GPIO03.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 2. GPIO02.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 1. GPIO01.
0 Active low.
1 Active high (default).
Deep sleep wake up signal polarity select 0. GPIO00.
0 Active low.
1 Active high (default).
Running
Suspended Running
Suspended Running
Suspended Running
e300 state
Table 24-7. PMC_PMCWSP field descriptions (continued)
Running
Periphery
Table
clocks
MPC5125 Microcontroller Reference Manual, Rev. 2
24-8. A reference on how the modes are entered and exited is provided
Table 24-8. MPC5125 Power Modes
Active
Active
Suspended Active
Suspended Suspended Active
Suspended Suspended Active
snooping
e300 bus
Active
Active
e300 time
registers
base
Description
Active
Active
Active
osc state
PLL,
Power Management Control Module (PMC)
Active
Active
Depends
Depends
Active
DRAM state
1,6
1,6
< 0.1 µS
< 0.1 µS
< 0.1 µS
< 0.1 µS
13,200 IPS clk cycles
Wake-up time
2
2
24-7