MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 525

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

20.2.2.2
20.2.2.3
There are six different types of IO_CTL_PAD registers. The drive strength of each pad and the functional
muxing is programmable. The following different types are used:
Freescale Semiconductor
Address: Base + 0x001
DATA_DS
GB_OBE
•
•
Reset
Field
Field
Standard with pull-up/down resistors (STD_PU)
— Functional muxing
— Programmable slew rate
— Programmable pull-up/down resistors
Standard with pull-up/down resistors and Schmitt trigger input (STD_PU_ST)
— Functional muxing
— Programmable slew rate
W
R
Global Output Enable Control Register (IO_CTL_GBOBE)
IO_CTL_PAD Registers Descriptions
DATA_DS controls the slew rate of all DRAM data pads (MDQ[31:0], MDM[3:0] and MDQS[3:0]).
000 DDR pad configuration 0
001 DDR pad configuration 1
010 DDR pad configuration 2
011 DDR pad configuration 3
100 Reserved
101 Reserved
110 DDR pad configuration 6
111 DDR pad configuration 7
Note: The configured DDR data pads is also valid for the GPIO/GPT lines in 16BIT mode configuration.
Note: DDR pad configurations are defined in the MPC5125 Microcontroller Data Sheet.
Global Output Enable
0 All default output pads except Test and boot related pads are driven to High Z.
1 Normal work.
This bit only controls function 0. It can be overridden by selecting a function other than function 0.
0
0
0
Figure 20-2. Global output enable control register (IO_CTL_GBOBE)
Table 20-2. IO_CTL_MEM field descriptions (continued)
1
0
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 20-3. IO_CTL_GBOBE field descriptions
0
0
2
0
0
3
Description
Description
0
0
4
0
0
5
Access: User read/write
0
0
6
GB_OBE
I/O Control
0
7
20-7