MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 788

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28.3.2.9
The SDHC Revision Number (SDHC_REV_NO) register is a read-only register displaying the revision
number of the module.
Figure 28-10
28-16
Address: Base + 0x1C
Reset
Reset
Field
NOB
W
W
R
R
16
0
0
0
0
SDHC Revision Number (SDHC_REV_NO) Register
shows the SDHC_REV_NO register and
Specifies the number of blocks in a block transfer. One block should be set if the data transfer command is a
single block transfer command or IO_RW_EXTEND (CMD53) in byte mode. For multi-block transfer command
to SD/MMC card and IO_RW_EXTEND (CMD53) in block mode to SDIO card, this register should be set the
block count software expects. Number of blocks can range from 0 to 65535.
For SD Memory card or a memory part of an SDIO combo card, send CMD12 to stop the multi-block transfer.
For an SDIO CMD53 in block mode when software needs to abort the transfer earlier, use CMD52 IO-Abort
to abort the transfer.
0x0000 0 block
0x0001 1 block
...
...
0xFFFF 65535 blocks
Note: The maximum transfer blocks is 65535. If software uses an infinite transfer command to transfer data,
17
0
0
0
1
such as the multi-block transfer command for memory card or the infinite block transfer CMD53 for SDIO
card, this register needs to be set to the real number of blocks expected to be transferred. Also, to abort
the transfer,the CMD12 or CMD52 IO-Abort must be used.
18
0
0
0
Figure 28-9. SDHC Number of Blocks (SDHC_NOB) Register
2
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 28-11. SDHC_NOB field descriptions
20
4
0
0
0
21
0
0
0
5
22
0
0
0
6
23
0
0
0
7
NOB
Description
Table 28-12
24
8
0
0
0
25
9
0
0
0
describes the bit field.
10
26
0
0
0
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0