MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 392

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
The buffer descriptors operate as a ring. The ETH_R_DES_START register defines the starting address
for receive BDs. The ETH_X_DES_START register defines the starting address for transmit BDs. The last
buffer descriptor in each ring is defined by the wrap (W) bit. When set, w indicates that the next descriptor
in the ring is at the location pointed to by ETH_R_DES_START and ETH_X_DES_START for the receive
and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; it is strongly
recommended that they are made 128-bit aligned.
14.5.1.1
Driver/DMA Operation with Transmit BDs
Typically, a transmit frame is divided between multiple buffers. An example is to have an Ethernet/802.3
header in the first buffer, an IP header in a second buffer, a TCP header in a third buffer, and an application
payload in the last buffer. The Ethernet MAC does not prepend the Ethernet header (destination address,
source address, length/type fields), so this must be provided by the driver in one of the transmit buffers.
The Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC
or by the driver is determined by the TC bit in the transmit BD, which must be set by the driver. When the
DMA of the transmit frame is complete, the DMA controller appends a control word to the frame. The
requirement for the control word is that the TC and ABC bits must be in the same position, as defined by
the transmit BD. The simplest solution is to copy the most significant 32 bits of the transmit BD into the
transmit FIFO at the end of the frame.
In a typical end station application, the TC bit always equals 1. For a switch/router application, the TC bit
may be 1 or 0, depending on what type of port the frame arrived on and whether the frame contents were
modified. The append bad CRC (ABC) bit is 0 unless an error has occurred (for example, a data parity
error during DMA transfer) that results in data corruption.
The driver (TxBD software producer) should set up TxBDs in such a way that a complete transmit frame
is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized
with pointer, length, and control (W, L, TC, ABC), and then the ownership (R) bits should be set equal to 1
in reverse order (BD 3, BD 2, BD 1) to ensure the complete frame is ready in memory before the DMA
begins. If the TxBDs are set up in order, the DMA Controller could DMA the first BD before the second
was made available, potentially causing a transmit FIFO underrun.
In the FEC, the driver notifies the DMA that new transmit frame(s) are available by writing to the
ETH_X_DES_ACTIVE register. When data is written to this register (data value is not significant), the
FEC RISC tells the DMA to read the next transmit BD in the ring. After the start, the RISC + DMA
continue reading and interpreting transmit BDs in order and DMA the associated buffers until a transmit
BD is encountered with the R bit cleared to 0. At this point, the FEC polls this BD one more time. If the
R bit equals 0 a second time, the RISC stops the transmit descriptor read process until software sets up
another transmit frame and writes to ETH_X_DES_ACTIVE.
When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R
(ownership) bit, indicating that the hardware consumer is finished with the buffer. A second driver task
(TxBD software consumer) processes the transmit descriptor ring and return buffers consumed by the
hardware to the free list.
MPC5125 Microcontroller Reference Manual, Rev. 2
14-36
Freescale Semiconductor