MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 720

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
In the codec soft modem mode, the PSC sends only one data word per frame.
Table 25-31
25-42
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BCLK Polarity SICR[ClkcPol]. When bit SICR[ClkPol] equals 0, data is shifted out on the rising
edge of bit clock and sampled on the falling edge of BCLK. Otherwise, data is shifted out on the
falling edge and sampled on rising edge of bit clock.
FrameSync width CTUR. Defines the number of BCLK while the FrameSync is active.
FrameSync length CCR[FrameSyncDiv]. Defines the number of BCLK until the next frame starts.
Data length SICR[SIM]. Defines the data with the receive and transmit data, 8-, 12-, 16-, 20-, 24-,
or 32-bit per word are possible. In codec 20 and 24 mode, each data sample uses an entire 32-bit
longword in the Tx FIFO. The least significant (right-hand) byte is not used. Data should be written
to the Tx FIFO four bytes at a time.
Delay of time slot 1 SICR[DTS1]. The PSC starts to send a sample at the leading edge of
FrameSync SICR[DTS1] if it equals 0 or 1 bit-clock cycle after the leading edge of FrameSync
SICR[DTS1] if it equals 1.
Data shift direction SICR[SHDIR]. Data shifted out LSB first if SICR[SHDIR] equals 1.
Otherwise, data shifts out MSB first if SICR[SHDIR] equals 0.
PSC in slave mode
16-bit soft modem mode
Data is sampled on the falling edge of BCLK
FrameSync is low true
MSB first, transfer starts with leading edge of FrameSync
Frame Sync
RX / TX
BCLK
shows an example how to configure PSC1 as:
DATA
Frame Sync Polarity
Start of Frame
Figure 25-47. Soft Modem Codec Interface Diagram
MPC5125 Microcontroller Reference Manual, Rev. 2
Frame Sync Width
Delay of Time Slot 1
Data Length
Frame Length
Data Bit Shift Direction
BCLK polarity
Start of Next Frame
Freescale Semiconductor