MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 504

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
In this case, the strategy to choose FDR value is like the one for standard mode device, but based on the
different timing requirements.
In
the IPS clock as a time unit. For example, from the table, if the SCL Divider equals 20, the SCL Period is
equal to 20 IPS clocks.
19-12
FDR Value
(0.0003) × [SCL (in kHz)] × (SCL Period) ≤ SDA Hold ≤ (0.0009) × [SCL (in kHz)] × (SCL Period) Eqn. 19-14
Table
0x20
0x21
0x22
0x23
0x24
0x00
0x01
0x25
0x02
0x26
0x27
0x03
0x60
0x04
0x61
0x28
0x05
0x62
0x63
0x29
and
and
and
19-6, the SCL Divider has the same meaning as SCL Period shown in
Divider
SCL
20
22
24
26
28
28
30
32
34
36
40
40
40
44
44
48
48
48
52
56
SCL Hold of START ≥ (0.0006) × [SCL (in kHz)] × (SCL Period)
SCL Hold of STOP ≥ (0.0006) × [SCL (in kHz)] × (SCL Period)
2
C)
SDA Hold
10
10
14
11
14
11
16
16
7
7
8
8
7
9
9
7
9
9
9
9
Table 19-6. I
MPC5125 Microcontroller Reference Manual, Rev. 2
SCL Hold
of START
10
10
11
12
13
14
16
16
12
18
14
18
20
16
18
22
6
7
8
9
2
C Frequency Divider Bit Selection
SCL Hold
of STOP
11
12
13
14
15
15
16
17
18
19
21
21
22
23
24
25
25
26
28
29
FDR Value
0xCC
0xCD
0xCB
0xAF
0xEF
0x8B
0x8C
0xB0
0x8D
0x13
0x4F
0x37
0x73
0x14
0x50
0x38
0x74
0xF0
0x15
0x51
Divider
SCL
480
480
512
512
512
512
512
512
576
576
576
576
640
640
640
640
640
640
640
640
SDA Hold
100
100
100
100
65
66
65
66
68
68
84
84
97
98
65
66
68
68
97
98
Figure
Freescale Semiconductor
SCL Hold
of START
19-10, which uses
238
236
254
252
248
248
232
232
286
284
280
280
318
316
312
312
318
316
312
312
Eqn. 19-15
Eqn. 19-16
SCL Hold
of STOP
241
242
257
258
260
260
260
260
289
290
292
292
321
322
324
324
321
322
324
324