MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 924

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.7.4
There are many situations where the host controller detects an empty list before the end of the micro-frame.
It is important to remember that under many circumstances the schedule traversal has stopped due to
Nak/Nyet responses from all endpoints.
An example of particular interest is when a start-split for a bulk endpoint occurs early in the micro-frame.
Given the EHCI simple traversal rules, the complete-split for that transaction may Nak/Nyet out quickly.
If it is the only item in the schedule, then the host controller ceases traversal of the Asynchronous schedule
early in the micro-frame. To provide reasonable service to this endpoint, the host controller should issue
the complete-split before the end of the current micro-frame, instead of waiting until the next micro-frame.
When the reason for host controller idling asynchronous schedule traversal is because of empty list
detection, it is mandatory the host controller implement a 'waking' method to resume traversal of the
asynchronous schedule. An example method is described below.
32.6.7.4.1
The reason for idling the host controller when the list is empty is to keep the host controller from
unnecessarily occupying too much memory bandwidth. How long should the host controller stay idle
before restarting?
The answer in this example is based on deriving a manifest constant, which is the amount of time the host
controller remains idle before restarting traversal. In this example, the manifest constant is called
AsyncSchedSleepTime, and has a value of 10 msec. The value is derived based on the analysis in
Section 32.6.7.4.2, “Example Derivation for AsyncSchedSleepTime.”
32-96
USB_ASYNCLISTADDR
•
•
USB_USBCMD
USB_USBSTS
Operational
Traverse the Asynchronous schedule until the either an End-Of-micro-Frame event occurs, or an
empty list is detected. If the event is an End-of-micro-Frame, go attempt to traverse the Periodic
schedule. If the event is an empty list, then set a sleep timer and go to a schedule sleep state.
When the sleep timer expires, set working context to the Asynchronous Schedule start condition
and go to schedule active state. The start context allows the HC to reload Nakcnt fields, etc. so the
HC has a chance to run for more than one iteration through the schedule.
Registers
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•
•
•
•
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Figure 32-58. Asynchronous Schedule List with Annotation to Mark Head of List
Restarting Asynchronous Schedule Before EOF
Example Method for Restarting Asynchronous Schedule Traversal
Horizontal Pointer
H
1
MPC5125 Microcontroller Reference Manual, Rev. 2
Reclamation Flag
List Head
Operational
Area
Typ T
01
1: Transaction Executed
0: Head of List Seen
0
Asynchronous Schedule
Horizontal Pointer
H
0
Operational
Area
Typ T
01 0
The traversal algorithm is simple:
Horizontal Pointer
H
0
Freescale Semiconductor
Operational
Area
Typ T
01 0