MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 98

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
4.6.4
The Reset Mode Register (RMR), shown in
4-12
Address: Base + 0x14
Reset
Reset
DPKILL
BMRS
PURE
Field
Field
SRS
HRS
W
W
R
R
16
0
0
0
0
0
Reset Mode Register (RMR)
The Reset Status Register accumulates reset events. This register returns to
its reset value only when power-on reset occurs.
Bus monitor reset status. When a bus monitor expire event (which causes a reset) is detected, BMRS is set
and remains set until the software clears it. BMRS is cleared by writing a logic 1 to it.
0 No bus monitor reset event has occurred.
1 A bus monitor reset event has occurred.
Soft reset status. When an external or internal soft reset event is detected, SRS is set and remains that way
until software clears it. SRS is cleared by writing a logic 1 to it.
0 No soft reset event has occurred.
1 A soft reset event has occurred.
Note: Soft reset induced by hard reset also sets this bit.
Hard reset status. When an external or internal hard reset event is detected, HRS is set and remains that way
until software clears it. HRS is cleared by writing a logic 1 to it.
0 No hard reset event has occurred.
1 A hard reset event has occurred.
Disable PLL Kill
0 Normal operation, during HRESET phase the system PLL is disabled to force a relock of the system PLL.
1 During HRESET phase the system PLL is still enabled; no relocking is required. The system PLL will be
PLL unlock reset enable
0 Reset is not generated when the system PLL unlocks.
1 Reset generated when the system PLL unlocks.
17
0
0
0
0
1
disabled if the PURE was the source of the reset.
18
0
0
0
0
2
19
0
0
0
0
3
Table 4-10. RSR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 4-5. Reset Mode Register (RMR)
20
4
0
0
0
0
Table 4-11. RMR field descriptions
21
0
0
0
0
5
Figure
22
0
0
0
0
6
NOTE
4-5, controls the internal reset sources.
23
0
0
0
0
7
Description
Description
24
8
0
0
0
0
25
9
0
0
0
0
10
26
0
0
0
0
KILL
DP
11
27
0
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
PURE CSRE
14
30
0
0
0
15
31
0
0
0