MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 851

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Field
SRI
URI
AAI
SEI
FRI
PCI
SLI
DCSuspend. This is a non-EHCI bit present on the OTG module only. When a device controller enters a
suspend state from an active state, this bit is set. This bit is only cleared by software writing a 1 to it. Only used
by the device controller.
0 Active.
1 Suspended.
Host mode:
This is a non-EHCI status bit. In host mode, this bit is set every 125 µs, provided the PHY clock is present and
running (i.e., the port is NOT suspended). The host controller driver can use it as a time base.
Device mode:
SOF Received. When the OTG controller detects a Start Of (micro) Frame, this bit is be set to a 1. When a
SOF is extremely late, the OTG controller automatically sets this bit to indicate an SOF was expected.
Therefore, this bit is set roughly every 1 msec in device FS mode and every 125 msec in HS mode and is
synchronized to the actual SOF received. Since the OTG controller is initialized to FS before connect, this bit
is set at an interval of 1 msec during the prelude to the connect and chirp.
Software writes a 1 to this bit to clear it.
USB Reset Received. This is a non-EHCI bit present on the OTG module only. When the OTG controller
detects a USB Reset and enters the default state, this bit is set to a 1. Software can write a 1 to this bit to clear
the USB Reset Received status bit. Only used by the device mode.
0 No reset received.
1 Reset received.
Interrupt on Async Advance. System software can force the controller to issue an interrupt the next time the
controller advances the asynchronous schedule by writing a 1 to the interrupt on async advance doorbell bit
in the USB_USBCMD register. This status bit indicates the assertion of that interrupt source. Only used by
the host mode.
0 No async advance interrupt.
1 Async advance interrupt.
System Error. This bit is set when an error is detected on the system bus. If the system error enable (SEE) bit
in the USB_USBINTR is set, an interrupt is generated. The interrupt and status bits remain asserted until
cleared by writing a 1 to this bit. Additionally, when in host mode, the RUN/STOP (RS) bit of the
USB_USBCMD register is cleared, effectively disabling the controller. For the OTG controller in device mode,
an interrupt is generated, but no other action is taken.
0 Normal operation.
1 Error.
Frame List Rollover. The controller sets this bit to 1 when the frame list index rolls over from its maximum value
to 0. The exact value at which the rollover occurs depends on the frame list size. For example, if the frame list
size (as programmed in the frame list size field of the USB_USBCMD register) is 1024, the frame index
register rolls over every time USB_FRINDEX [13] toggles. Similarly, if the size is 512, the controller sets this
bit to a 1 every time FHINDEX [12] toggles. Used only by the host mode.
Host mode:
Port Change Detect. The controller sets this bit to 1 when on any port a connect status occurs, a port
enable/disable change occurs, or the force port resume bit is set as the result of a J-K transition on the
suspended port.
Device mode:
The OTG controller sets this bit to 1 when it enters the full or high-speed operational state. When the USB
exits full or high-speed operation states due to reset or suspend events, the notification mechanisms are the
USB reset received bit and the DCSuspend bits respectively. The device controller detects resume signalling
only.
This bit is not EHCI compatible.
Table 32-17. USB_USBSTS field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Description
Universal Serial Bus Interface with On-The-Go
32-23